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FpgaRegs.h
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00010 #ifndef __FPGAREGS_H__APOGEE_APN__
00011 #define __FPGAREGS_H__APOGEE_APN__
00012
00013
00014 #define FPGA_TOTAL_REGISTER_COUNT 103
00015
00016
00017 #define FPGA_REG_COMMAND_A 0
00018 #define FPGA_BIT_CMD_EXPOSE 0x0001
00019 #define FPGA_BIT_CMD_DARK 0x0002
00020 #define FPGA_BIT_CMD_TEST 0x0004
00021 #define FPGA_BIT_CMD_TDI 0x0008
00022 #define FPGA_BIT_CMD_FLUSH 0x0010
00023 #define FPGA_BIT_CMD_TRIGGER_EXPOSE 0x0020
00024
00025 #define FPGA_REG_COMMAND_B 1
00026 #define FPGA_BIT_CMD_RESET 0x0002
00027 #define FPGA_BIT_CMD_CLEAR_ALL 0x0010
00028 #define FPGA_BIT_CMD_END_EXPOSURE 0x0080
00029 #define FPGA_BIT_CMD_RAMP_TO_SETPOINT 0x0200
00030 #define FPGA_BIT_CMD_RAMP_TO_AMBIENT 0x0400
00031 #define FPGA_BIT_CMD_START_TEMP_READ 0x2000
00032 #define FPGA_BIT_CMD_DAC_LOAD 0x4000
00033 #define FPGA_BIT_CMD_AD_CONFIG 0x8000
00034
00035 #define FPGA_REG_OP_A 2
00036 #define FPGA_BIT_LED_DISABLE 0x0001
00037 #define FPGA_BIT_PAUSE_TIMER 0x0002
00038 #define FPGA_BIT_RATIO 0x0004
00039 #define FPGA_BIT_DELAY_MODE 0x0008
00040 #define FPGA_BIT_P_CLK_MODE 0x0010
00041 #define FPGA_BIT_LED_EXPOSE_DISABLE 0x0020
00042 #define FPGA_BIT_DISABLE_H_CLK 0x0040
00043 #define FPGA_BIT_SHUTTER_AMP_CONTROL 0x0080
00044 #define FPGA_BIT_HALT_DISABLE 0x0100
00045 #define FPGA_BIT_SHUTTER_MODE 0x0200
00046 #define FPGA_BIT_DIGITIZATION_RES 0x0400
00047 #define FPGA_BIT_FORCE_SHUTTER 0x0800
00048 #define FPGA_BIT_DISABLE_SHUTTER 0x1000
00049 #define FPGA_BIT_TEMP_SUSPEND 0x2000
00050 #define FPGA_BIT_SHUTTER_SOURCE 0x4000
00051 #define FPGA_BIT_TEST_MODE 0x8000
00052
00053 #define FPGA_REG_OP_B 3
00054 #define FPGA_BIT_HCLAMP_ENABLE 0x0008
00055 #define FPGA_BIT_HSKIP_ENABLE 0x0010
00056 #define FPGA_BIT_HRAM_ENABLE 0x0020
00057 #define FPGA_BIT_VRAM_ENABLE 0x0040
00058 #define FPGA_BIT_DAC_SELECT_ZERO 0x0080
00059 #define FPGA_BIT_DAC_SELECT_ONE 0x0100
00060 #define FPGA_BIT_AD_SIMULATION 0x8000
00061
00062 #define FPGA_REG_TIMER_UPPER 4
00063 #define FPGA_REG_TIMER_LOWER 5
00064
00065 #define FPGA_REG_HRAM_INPUT 6
00066 #define FPGA_REG_VRAM_INPUT 7
00067
00068 #define FPGA_REG_HRAM_INV_MASK 8
00069 #define FPGA_REG_VRAM_INV_MASK 9
00070
00071 #define FPGA_REG_HCLAMP_INPUT 10
00072 #define FPGA_REG_HSKIP_INPUT 11
00073
00074 #define FPGA_REG_PRECLAMP_SKIP_COUNT 12
00075 #define FPGA_REG_CLAMP_COUNT 13
00076 #define FPGA_REG_PREROI_SKIP_COUNT 14
00077 #define FPGA_REG_ROI_COUNT 15
00078 #define FPGA_REG_POSTROI_SKIP_COUNT 16
00079 #define FPGA_REG_OVERSCAN_COUNT 17
00080 #define FPGA_REG_IMAGE_COUNT 18
00081
00082 #define FPGA_REG_VFLUSH_BINNING 19
00083
00084 #define FPGA_REG_SHUTTER_CLOSE_DELAY 20
00085
00086 #define FPGA_REG_POSTOVERSCAN_SKIP_COUNT 21
00087
00088 #define FPGA_REG_SHUTTER_STROBE_POSITION 23
00089 #define FPGA_REG_SHUTTER_STROBE_PERIOD 24
00090
00091 #define FPGA_REG_FAN_SPEED_CONTROL 25
00092 #define FPGA_REG_LED_DRIVE 26
00093 #define FPGA_REG_SUBSTRATE_ADJUST 27
00094 #define FPGA_MASK_FAN_SPEED_CONTROL 0x0FFF
00095 #define FPGA_MASK_LED_ILLUMINATION 0x0FFF
00096 #define FPGA_MASK_SUBSTRATE_ADJUST 0x0FFF
00097
00098 #define FPGA_REG_TEST_COUNT_UPPER 28
00099 #define FPGA_REG_TEST_COUNT_LOWER 29
00100
00101 #define FPGA_REG_A1_ROW_COUNT 30
00102 #define FPGA_REG_A1_VBINNING 31
00103 #define FPGA_REG_A2_ROW_COUNT 32
00104 #define FPGA_REG_A2_VBINNING 33
00105 #define FPGA_REG_A3_ROW_COUNT 34
00106 #define FPGA_REG_A3_VBINNING 35
00107
00108 #define FPGA_MASK_VBINNING 0x0FFF
00109 #define FPGA_BIT_ARRAY_DIGITIZE 0x1000
00110 #define FPGA_BIT_ARRAY_FASTDUMP 0x4000
00111
00112 #define FPGA_REG_SEQUENCE_DELAY 47
00113 #define FPGA_REG_TDI_RATE 48
00114
00115 #define FPGA_REG_IO_PORT_WRITE 49
00116
00117 #define FPGA_REG_IO_PORT_DIRECTION 50
00118 #define FPGA_MASK_IO_PORT_DIRECTION 0x003F
00119
00120 #define FPGA_REG_IO_PORT_ASSIGNMENT 51
00121 #define FPGA_MASK_IO_PORT_ASSIGNMENT 0x003F
00122
00123 #define FPGA_REG_LED_SELECT 52
00124 #define FPGA_MASK_LED_SELECT_A 0x000F
00125 #define FPGA_MASK_LED_SELECT_B 0x00F0
00126 #define FPGA_BIT_LED_EXPOSE 0x0001
00127 #define FPGA_BIT_LED_IMAGE_ACTIVE 0x0002
00128 #define FPGA_BIT_LED_FLUSHING 0x0004
00129 #define FPGA_BIT_LED_TRIGGER_WAIT 0x0008
00130 #define FPGA_BIT_LED_EXT_TRIGGER 0x0010
00131 #define FPGA_BIT_LED_EXT_SHUTTER_INPUT 0x0020
00132 #define FPGA_BIT_LED_EXT_START_READOUT 0x0040
00133 #define FPGA_BIT_LED_AT_TEMP 0x0080
00134
00135 #define FPGA_REG_SCRATCH 53
00136
00137 #define FPGA_REG_TDI_COUNT 54
00138
00139 #define FPGA_REG_TEMP_DESIRED 55
00140
00141 #define FPGA_REG_TEMP_RAMP_DOWN_A 57
00142 #define FPGA_REG_TEMP_RAMP_DOWN_B 58
00143 #define FPGA_REG_TEMP_BACKOFF 60
00144 #define FPGA_REG_TEMP_COOLER_OVERRIDE 61
00145 #define FPGA_MASK_TEMP_PARAMS 0x0FFF // 12 bits
00146
00147 #define FPGA_REG_AD_CONFIG_DATA 62
00148 #define FPGA_MASK_AD_GAIN 0x07FF // 11 bits
00149
00150 #define FPGA_REG_IO_PORT_READ 90
00151 #define FPGA_MASK_IO_PORT_DATA 0x003F
00152
00153 #define FPGA_REG_GENERAL_STATUS 91
00154 #define FPGA_BIT_STATUS_IMAGE_EXPOSING 0x0001
00155 #define FPGA_BIT_STATUS_IMAGING_ACTIVE 0x0002
00156 #define FPGA_BIT_STATUS_DATA_HALTED 0x0004
00157 #define FPGA_BIT_STATUS_IMAGE_DONE 0x0008
00158 #define FPGA_BIT_STATUS_FLUSHING 0x0010
00159 #define FPGA_BIT_STATUS_WAITING_TRIGGER 0x0020
00160 #define FPGA_BIT_STATUS_SHUTTER_OPEN 0x0040
00161 #define FPGA_BIT_STATUS_PATTERN_ERROR 0x0080
00162 #define FPGA_BIT_STATUS_TEMP_SUSPEND_ACK 0x0100
00163 #define FPGA_BIT_STATUS_TEMP_REVISION 0x2000
00164 #define FPGA_BIT_STATUS_TEMP_AT_TEMP 0x4000
00165 #define FPGA_BIT_STATUS_TEMP_ACTIVE 0x8000
00166
00167 #define FPGA_REG_TEMP_HEATSINK 93
00168 #define FPGA_REG_TEMP_CCD 94
00169 #define FPGA_REG_TEMP_DRIVE 95
00170
00171 #define FPGA_REG_INPUT_VOLTAGE 96
00172 #define FPGA_MASK_INPUT_VOLTAGE 0x0FFF
00173
00174 #define FPGA_REG_TEMP_REVISED 97
00175
00176 #define FPGA_REG_FIFO_DATA 98
00177 #define FPGA_REG_FIFO_STATUS 99
00178
00179 #define FPGA_REG_CAMERA_ID 100
00180 #define FPGA_MASK_CAMERA_ID 0x007F
00181
00182 #define FPGA_REG_FIRMWARE_REV 101
00183
00184 #define FPGA_REG_FIFO_FULL_COUNT 102
00185 #define FPGA_REG_FIFO_EMPTY_COUNT 103
00186
00187 #define FPGA_REG_TDI_COUNTER 104
00188 #define FPGA_REG_SEQUENCE_COUNTER 105
00189
00190 #endif