KWayland

drm_fourcc.h
1 /*
2  SPDX-FileCopyrightText: 2011 Intel Corporation
3 
4  SPDX-License-Identifier: MIT
5 */
6 
7 #ifndef DRM_FOURCC_H
8 #define DRM_FOURCC_H
9 
10 //#include "drm.h"
11 
12 // These typedefs are copied from drm.h
13 typedef uint32_t __u32;
14 typedef uint64_t __u64;
15 
16 #if defined(__cplusplus)
17 extern "C" {
18 #endif
19 
20 #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
21  ((__u32)(c) << 16) | ((__u32)(d) << 24))
22 
23 #define DRM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of little endian */
24 
25 /* color index */
26 #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
27 
28 /* 8 bpp Red */
29 #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
30 
31 /* 16 bpp Red */
32 #define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */
33 
34 /* 16 bpp RG */
35 #define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */
36 #define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */
37 
38 /* 32 bpp RG */
39 #define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */
40 #define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */
41 
42 /* 8 bpp RGB */
43 #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
44 #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
45 
46 /* 16 bpp RGB */
47 #define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */
48 #define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */
49 #define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */
50 #define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */
51 
52 #define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */
53 #define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */
54 #define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */
55 #define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */
56 
57 #define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */
58 #define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */
59 #define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */
60 #define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */
61 
62 #define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */
63 #define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */
64 #define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */
65 #define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */
66 
67 #define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */
68 #define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */
69 
70 /* 24 bpp RGB */
71 #define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */
72 #define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */
73 
74 /* 32 bpp RGB */
75 #define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */
76 #define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */
77 #define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */
78 #define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */
79 
80 #define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */
81 #define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */
82 #define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */
83 #define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */
84 
85 #define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */
86 #define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */
87 #define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */
88 #define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */
89 
90 #define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */
91 #define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */
92 #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
93 #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
94 
95 /* packed YCbCr */
96 #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
97 #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
98 #define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */
99 #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
100 
101 #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
102 
103 /*
104  * 2 plane RGB + A
105  * index 0 = RGB plane, same format as the corresponding non _A8 format has
106  * index 1 = A plane, [7:0] A
107  */
108 #define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8')
109 #define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8')
110 #define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8')
111 #define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8')
112 #define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8')
113 #define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8')
114 #define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8')
115 #define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8')
116 
117 /*
118  * 2 plane YCbCr
119  * index 0 = Y plane, [7:0] Y
120  * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian
121  * or
122  * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian
123  */
124 #define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */
125 #define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */
126 #define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */
127 #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
128 #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
129 #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
130 
131 /*
132  * 3 plane YCbCr
133  * index 0: Y plane, [7:0] Y
134  * index 1: Cb plane, [7:0] Cb
135  * index 2: Cr plane, [7:0] Cr
136  * or
137  * index 1: Cr plane, [7:0] Cr
138  * index 2: Cb plane, [7:0] Cb
139  */
140 #define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */
141 #define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */
142 #define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */
143 #define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */
144 #define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */
145 #define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */
146 #define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */
147 #define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */
148 #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */
149 #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */
150 
151 
152 /*
153  * Format Modifiers:
154  *
155  * Format modifiers describe, typically, a re-ordering or modification
156  * of the data in a plane of an FB. This can be used to express tiled/
157  * swizzled formats, or compression, or a combination of the two.
158  *
159  * The upper 8 bits of the format modifier are a vendor-id as assigned
160  * below. The lower 56 bits are assigned as vendor sees fit.
161  */
162 
163 /* Vendor Ids: */
164 #define DRM_FORMAT_MOD_NONE 0
165 #define DRM_FORMAT_MOD_VENDOR_NONE 0
166 #define DRM_FORMAT_MOD_VENDOR_INTEL 0x01
167 #define DRM_FORMAT_MOD_VENDOR_AMD 0x02
168 #define DRM_FORMAT_MOD_VENDOR_NV 0x03
169 #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
170 #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05
171 #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
172 #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
173 /* add more to the end as needed */
174 
175 #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
176 
177 #define fourcc_mod_code(vendor, val) \
178  ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | (val & 0x00ffffffffffffffULL))
179 
180 /*
181  * Format Modifier tokens:
182  *
183  * When adding a new token please document the layout with a code comment,
184  * similar to the fourcc codes above. drm_fourcc.h is considered the
185  * authoritative source for all of these.
186  */
187 
188 /*
189  * Invalid Modifier
190  *
191  * This modifier can be used as a sentinel to terminate the format modifiers
192  * list, or to initialize a variable with an invalid modifier. It might also be
193  * used to report an error back to userspace for certain APIs.
194  */
195 #define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED)
196 
197 /*
198  * Linear Layout
199  *
200  * Just plain linear layout. Note that this is different from no specifying any
201  * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl),
202  * which tells the driver to also take driver-internal information into account
203  * and so might actually result in a tiled framebuffer.
204  */
205 #define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0)
206 
207 /* Intel framebuffer modifiers */
208 
209 /*
210  * Intel X-tiling layout
211  *
212  * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
213  * in row-major layout. Within the tile bytes are laid out row-major, with
214  * a platform-dependent stride. On top of that the memory can apply
215  * platform-depending swizzling of some higher address bits into bit6.
216  *
217  * This format is highly platforms specific and not useful for cross-driver
218  * sharing. It exists since on a given platform it does uniquely identify the
219  * layout in a simple way for i915-specific userspace.
220  */
221 #define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1)
222 
223 /*
224  * Intel Y-tiling layout
225  *
226  * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
227  * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
228  * chunks column-major, with a platform-dependent height. On top of that the
229  * memory can apply platform-depending swizzling of some higher address bits
230  * into bit6.
231  *
232  * This format is highly platforms specific and not useful for cross-driver
233  * sharing. It exists since on a given platform it does uniquely identify the
234  * layout in a simple way for i915-specific userspace.
235  */
236 #define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2)
237 
238 /*
239  * Intel Yf-tiling layout
240  *
241  * This is a tiled layout using 4Kb tiles in row-major layout.
242  * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
243  * are arranged in four groups (two wide, two high) with column-major layout.
244  * Each group therefore consits out of four 256 byte units, which are also laid
245  * out as 2x2 column-major.
246  * 256 byte units are made out of four 64 byte blocks of pixels, producing
247  * either a square block or a 2:1 unit.
248  * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width
249  * in pixel depends on the pixel depth.
250  */
251 #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)
252 
253 /*
254  * Intel color control surface (CCS) for render compression
255  *
256  * The framebuffer format must be one of the 8:8:8:8 RGB formats.
257  * The main surface will be plane index 0 and must be Y/Yf-tiled,
258  * the CCS will be plane index 1.
259  *
260  * Each CCS tile matches a 1024x512 pixel area of the main surface.
261  * To match certain aspects of the 3D hardware the CCS is
262  * considered to be made up of normal 128Bx32 Y tiles, Thus
263  * the CCS pitch must be specified in multiples of 128 bytes.
264  *
265  * In reality the CCS tile appears to be a 64Bx64 Y tile, composed
266  * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks.
267  * But that fact is not relevant unless the memory is accessed
268  * directly.
269  */
270 #define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)
271 #define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5)
272 
273 /*
274  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
275  *
276  * Macroblocks are laid in a Z-shape, and each pixel data is following the
277  * standard NV12 style.
278  * As for NV12, an image is the result of two frame buffers: one for Y,
279  * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer).
280  * Alignment requirements are (for each buffer):
281  * - multiple of 128 pixels for the width
282  * - multiple of 32 pixels for the height
283  *
284  * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html
285  */
286 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
287 
288 /* Vivante framebuffer modifiers */
289 
290 /*
291  * Vivante 4x4 tiling layout
292  *
293  * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
294  * layout.
295  */
296 #define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1)
297 
298 /*
299  * Vivante 64x64 super-tiling layout
300  *
301  * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
302  * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
303  * major layout.
304  *
305  * For more information: see
306  * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
307  */
308 #define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2)
309 
310 /*
311  * Vivante 4x4 tiling layout for dual-pipe
312  *
313  * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
314  * different base address. Offsets from the base addresses are therefore halved
315  * compared to the non-split tiled layout.
316  */
317 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3)
318 
319 /*
320  * Vivante 64x64 super-tiling layout for dual-pipe
321  *
322  * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
323  * starts at a different base address. Offsets from the base addresses are
324  * therefore halved compared to the non-split super-tiled layout.
325  */
326 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
327 
328 /* NVIDIA Tegra frame buffer modifiers */
329 
330 /*
331  * Some modifiers take parameters, for example the number of vertical GOBs in
332  * a block. Reserve the lower 32 bits for parameters
333  */
334 #define __fourcc_mod_tegra_mode_shift 32
335 #define fourcc_mod_tegra_code(val, params) \
336  fourcc_mod_code(NV, ((((__u64)val) << __fourcc_mod_tegra_mode_shift) | params))
337 #define fourcc_mod_tegra_mod(m) \
338  (m & ~((1ULL << __fourcc_mod_tegra_mode_shift) - 1))
339 #define fourcc_mod_tegra_param(m) \
340  (m & ((1ULL << __fourcc_mod_tegra_mode_shift) - 1))
341 
342 /*
343  * Tegra Tiled Layout, used by Tegra 2, 3 and 4.
344  *
345  * Pixels are arranged in simple tiles of 16 x 16 bytes.
346  */
347 #define NV_FORMAT_MOD_TEGRA_TILED fourcc_mod_tegra_code(1, 0)
348 
349 /*
350  * Tegra 16Bx2 Block Linear layout, used by TK1/TX1
351  *
352  * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked
353  * vertically by a power of 2 (1 to 32 GOBs) to form a block.
354  *
355  * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
356  *
357  * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically.
358  * Valid values are:
359  *
360  * 0 == ONE_GOB
361  * 1 == TWO_GOBS
362  * 2 == FOUR_GOBS
363  * 3 == EIGHT_GOBS
364  * 4 == SIXTEEN_GOBS
365  * 5 == THIRTYTWO_GOBS
366  *
367  * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
368  * in full detail.
369  */
370 #define NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(v) fourcc_mod_tegra_code(2, v)
371 
372 /*
373  * Broadcom VC4 "T" format
374  *
375  * This is the primary layout that the V3D GPU can texture from (it
376  * can't do linear). The T format has:
377  *
378  * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4
379  * pixels at 32 bit depth.
380  *
381  * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
382  * 16x16 pixels).
383  *
384  * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On
385  * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows
386  * they're (TR, BR, BL, TL), where bottom left is start of memory.
387  *
388  * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
389  * tiles) or right-to-left (odd rows of 4k tiles).
390  */
391 #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
392 
393 #if defined(__cplusplus)
394 }
395 #endif
396 
397 #endif /* DRM_FOURCC_H */
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