KWayland

drm_fourcc.h
1 /*
2  SPDX-FileCopyrightText: 2011 Intel Corporation
3 
4  SPDX-License-Identifier: MIT
5 */
6 
7 #ifndef DRM_FOURCC_H
8 #define DRM_FOURCC_H
9 
10 // clang-format off
11 
12 //#include "drm.h"
13 
14 // These typedefs are copied from drm.h
15 typedef uint32_t __u32;
16 typedef uint64_t __u64;
17 
18 #if defined(__cplusplus)
19 extern "C" {
20 #endif
21 
22 #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
23  ((__u32)(c) << 16) | ((__u32)(d) << 24))
24 
25 #define DRM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of little endian */
26 
27 /* color index */
28 #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
29 
30 /* 8 bpp Red */
31 #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
32 
33 /* 16 bpp Red */
34 #define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */
35 
36 /* 16 bpp RG */
37 #define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */
38 #define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */
39 
40 /* 32 bpp RG */
41 #define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */
42 #define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */
43 
44 /* 8 bpp RGB */
45 #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
46 #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
47 
48 /* 16 bpp RGB */
49 #define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */
50 #define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */
51 #define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */
52 #define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */
53 
54 #define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */
55 #define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */
56 #define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */
57 #define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */
58 
59 #define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */
60 #define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */
61 #define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */
62 #define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */
63 
64 #define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */
65 #define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */
66 #define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */
67 #define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */
68 
69 #define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */
70 #define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */
71 
72 /* 24 bpp RGB */
73 #define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */
74 #define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */
75 
76 /* 32 bpp RGB */
77 #define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */
78 #define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */
79 #define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */
80 #define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */
81 
82 #define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */
83 #define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */
84 #define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */
85 #define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */
86 
87 #define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */
88 #define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */
89 #define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */
90 #define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */
91 
92 #define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */
93 #define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */
94 #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
95 #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
96 
97 /* packed YCbCr */
98 #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
99 #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
100 #define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */
101 #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
102 
103 #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
104 
105 /*
106  * 2 plane RGB + A
107  * index 0 = RGB plane, same format as the corresponding non _A8 format has
108  * index 1 = A plane, [7:0] A
109  */
110 #define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8')
111 #define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8')
112 #define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8')
113 #define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8')
114 #define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8')
115 #define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8')
116 #define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8')
117 #define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8')
118 
119 /*
120  * 2 plane YCbCr
121  * index 0 = Y plane, [7:0] Y
122  * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian
123  * or
124  * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian
125  */
126 #define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */
127 #define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */
128 #define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */
129 #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
130 #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
131 #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
132 
133 /*
134  * 3 plane YCbCr
135  * index 0: Y plane, [7:0] Y
136  * index 1: Cb plane, [7:0] Cb
137  * index 2: Cr plane, [7:0] Cr
138  * or
139  * index 1: Cr plane, [7:0] Cr
140  * index 2: Cb plane, [7:0] Cb
141  */
142 #define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */
143 #define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */
144 #define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */
145 #define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */
146 #define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */
147 #define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */
148 #define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */
149 #define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */
150 #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */
151 #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */
152 
153 
154 /*
155  * Format Modifiers:
156  *
157  * Format modifiers describe, typically, a re-ordering or modification
158  * of the data in a plane of an FB. This can be used to express tiled/
159  * swizzled formats, or compression, or a combination of the two.
160  *
161  * The upper 8 bits of the format modifier are a vendor-id as assigned
162  * below. The lower 56 bits are assigned as vendor sees fit.
163  */
164 
165 /* Vendor Ids: */
166 #define DRM_FORMAT_MOD_NONE 0
167 #define DRM_FORMAT_MOD_VENDOR_NONE 0
168 #define DRM_FORMAT_MOD_VENDOR_INTEL 0x01
169 #define DRM_FORMAT_MOD_VENDOR_AMD 0x02
170 #define DRM_FORMAT_MOD_VENDOR_NV 0x03
171 #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
172 #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05
173 #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
174 #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
175 /* add more to the end as needed */
176 
177 #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
178 
179 #define fourcc_mod_code(vendor, val) \
180  ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | (val & 0x00ffffffffffffffULL))
181 
182 /*
183  * Format Modifier tokens:
184  *
185  * When adding a new token please document the layout with a code comment,
186  * similar to the fourcc codes above. drm_fourcc.h is considered the
187  * authoritative source for all of these.
188  */
189 
190 /*
191  * Invalid Modifier
192  *
193  * This modifier can be used as a sentinel to terminate the format modifiers
194  * list, or to initialize a variable with an invalid modifier. It might also be
195  * used to report an error back to userspace for certain APIs.
196  */
197 #define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED)
198 
199 /*
200  * Linear Layout
201  *
202  * Just plain linear layout. Note that this is different from no specifying any
203  * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl),
204  * which tells the driver to also take driver-internal information into account
205  * and so might actually result in a tiled framebuffer.
206  */
207 #define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0)
208 
209 /* Intel framebuffer modifiers */
210 
211 /*
212  * Intel X-tiling layout
213  *
214  * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
215  * in row-major layout. Within the tile bytes are laid out row-major, with
216  * a platform-dependent stride. On top of that the memory can apply
217  * platform-depending swizzling of some higher address bits into bit6.
218  *
219  * This format is highly platforms specific and not useful for cross-driver
220  * sharing. It exists since on a given platform it does uniquely identify the
221  * layout in a simple way for i915-specific userspace.
222  */
223 #define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1)
224 
225 /*
226  * Intel Y-tiling layout
227  *
228  * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
229  * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
230  * chunks column-major, with a platform-dependent height. On top of that the
231  * memory can apply platform-depending swizzling of some higher address bits
232  * into bit6.
233  *
234  * This format is highly platforms specific and not useful for cross-driver
235  * sharing. It exists since on a given platform it does uniquely identify the
236  * layout in a simple way for i915-specific userspace.
237  */
238 #define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2)
239 
240 /*
241  * Intel Yf-tiling layout
242  *
243  * This is a tiled layout using 4Kb tiles in row-major layout.
244  * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
245  * are arranged in four groups (two wide, two high) with column-major layout.
246  * Each group therefore consists out of four 256 byte units, which are also laid
247  * out as 2x2 column-major.
248  * 256 byte units are made out of four 64 byte blocks of pixels, producing
249  * either a square block or a 2:1 unit.
250  * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width
251  * in pixel depends on the pixel depth.
252  */
253 #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)
254 
255 /*
256  * Intel color control surface (CCS) for render compression
257  *
258  * The framebuffer format must be one of the 8:8:8:8 RGB formats.
259  * The main surface will be plane index 0 and must be Y/Yf-tiled,
260  * the CCS will be plane index 1.
261  *
262  * Each CCS tile matches a 1024x512 pixel area of the main surface.
263  * To match certain aspects of the 3D hardware the CCS is
264  * considered to be made up of normal 128Bx32 Y tiles, Thus
265  * the CCS pitch must be specified in multiples of 128 bytes.
266  *
267  * In reality the CCS tile appears to be a 64Bx64 Y tile, composed
268  * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks.
269  * But that fact is not relevant unless the memory is accessed
270  * directly.
271  */
272 #define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)
273 #define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5)
274 
275 /*
276  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
277  *
278  * Macroblocks are laid in a Z-shape, and each pixel data is following the
279  * standard NV12 style.
280  * As for NV12, an image is the result of two frame buffers: one for Y,
281  * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer).
282  * Alignment requirements are (for each buffer):
283  * - multiple of 128 pixels for the width
284  * - multiple of 32 pixels for the height
285  *
286  * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html
287  */
288 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
289 
290 /* Vivante framebuffer modifiers */
291 
292 /*
293  * Vivante 4x4 tiling layout
294  *
295  * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
296  * layout.
297  */
298 #define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1)
299 
300 /*
301  * Vivante 64x64 super-tiling layout
302  *
303  * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
304  * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
305  * major layout.
306  *
307  * For more information: see
308  * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
309  */
310 #define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2)
311 
312 /*
313  * Vivante 4x4 tiling layout for dual-pipe
314  *
315  * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
316  * different base address. Offsets from the base addresses are therefore halved
317  * compared to the non-split tiled layout.
318  */
319 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3)
320 
321 /*
322  * Vivante 64x64 super-tiling layout for dual-pipe
323  *
324  * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
325  * starts at a different base address. Offsets from the base addresses are
326  * therefore halved compared to the non-split super-tiled layout.
327  */
328 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
329 
330 /* NVIDIA Tegra frame buffer modifiers */
331 
332 /*
333  * Some modifiers take parameters, for example the number of vertical GOBs in
334  * a block. Reserve the lower 32 bits for parameters
335  */
336 #define __fourcc_mod_tegra_mode_shift 32
337 #define fourcc_mod_tegra_code(val, params) \
338  fourcc_mod_code(NV, ((((__u64)val) << __fourcc_mod_tegra_mode_shift) | params))
339 #define fourcc_mod_tegra_mod(m) \
340  (m & ~((1ULL << __fourcc_mod_tegra_mode_shift) - 1))
341 #define fourcc_mod_tegra_param(m) \
342  (m & ((1ULL << __fourcc_mod_tegra_mode_shift) - 1))
343 
344 /*
345  * Tegra Tiled Layout, used by Tegra 2, 3 and 4.
346  *
347  * Pixels are arranged in simple tiles of 16 x 16 bytes.
348  */
349 #define NV_FORMAT_MOD_TEGRA_TILED fourcc_mod_tegra_code(1, 0)
350 
351 /*
352  * Tegra 16Bx2 Block Linear layout, used by TK1/TX1
353  *
354  * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked
355  * vertically by a power of 2 (1 to 32 GOBs) to form a block.
356  *
357  * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
358  *
359  * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically.
360  * Valid values are:
361  *
362  * 0 == ONE_GOB
363  * 1 == TWO_GOBS
364  * 2 == FOUR_GOBS
365  * 3 == EIGHT_GOBS
366  * 4 == SIXTEEN_GOBS
367  * 5 == THIRTYTWO_GOBS
368  *
369  * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
370  * in full detail.
371  */
372 #define NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(v) fourcc_mod_tegra_code(2, v)
373 
374 /*
375  * Broadcom VC4 "T" format
376  *
377  * This is the primary layout that the V3D GPU can texture from (it
378  * can't do linear). The T format has:
379  *
380  * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4
381  * pixels at 32 bit depth.
382  *
383  * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
384  * 16x16 pixels).
385  *
386  * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On
387  * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows
388  * they're (TR, BR, BL, TL), where bottom left is start of memory.
389  *
390  * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
391  * tiles) or right-to-left (odd rows of 4k tiles).
392  */
393 #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
394 
395 #if defined(__cplusplus)
396 }
397 #endif
398 
399 #endif /* DRM_FOURCC_H */
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