KWaylandServer

drm_fourcc.h
1 /*
2  SPDX-FileCopyrightText: 2011 Intel Corporation
3 
4  SPDX-License-Identifier: MIT
5 */
6 
7 #ifndef DRM_FOURCC_H
8 #define DRM_FOURCC_H
9 
10 //#include "drm.h"
11 
12 // These typedefs are copied from drm.h
13 typedef uint32_t __u32;
14 typedef uint64_t __u64;
15 
16 #if defined(__cplusplus)
17 extern "C" {
18 #endif
19 
20 #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | ((__u32)(c) << 16) | ((__u32)(d) << 24))
21 
22 #define DRM_FORMAT_BIG_ENDIAN (1 << 31) /* format is big endian instead of little endian */
23 
24 /* color index */
25 #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
26 
27 /* 8 bpp Red */
28 #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
29 
30 /* 16 bpp Red */
31 #define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */
32 
33 /* 16 bpp RG */
34 #define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */
35 #define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */
36 
37 /* 32 bpp RG */
38 #define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */
39 #define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */
40 
41 /* 8 bpp RGB */
42 #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
43 #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
44 
45 /* 16 bpp RGB */
46 #define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */
47 #define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */
48 #define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */
49 #define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */
50 
51 #define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */
52 #define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */
53 #define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */
54 #define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */
55 
56 #define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */
57 #define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */
58 #define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */
59 #define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */
60 
61 #define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */
62 #define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */
63 #define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */
64 #define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */
65 
66 #define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */
67 #define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */
68 
69 /* 24 bpp RGB */
70 #define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */
71 #define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */
72 
73 /* 32 bpp RGB */
74 #define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */
75 #define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */
76 #define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */
77 #define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */
78 
79 #define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */
80 #define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */
81 #define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */
82 #define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */
83 
84 #define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */
85 #define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */
86 #define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */
87 #define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */
88 
89 #define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */
90 #define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */
91 #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
92 #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
93 
94 /* packed YCbCr */
95 #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
96 #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
97 #define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */
98 #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
99 
100 #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
101 
102 /*
103  * 2 plane RGB + A
104  * index 0 = RGB plane, same format as the corresponding non _A8 format has
105  * index 1 = A plane, [7:0] A
106  */
107 #define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8')
108 #define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8')
109 #define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8')
110 #define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8')
111 #define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8')
112 #define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8')
113 #define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8')
114 #define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8')
115 
116 /*
117  * 2 plane YCbCr
118  * index 0 = Y plane, [7:0] Y
119  * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian
120  * or
121  * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian
122  */
123 #define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */
124 #define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */
125 #define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */
126 #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
127 #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
128 #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
129 
130 /*
131  * 3 plane YCbCr
132  * index 0: Y plane, [7:0] Y
133  * index 1: Cb plane, [7:0] Cb
134  * index 2: Cr plane, [7:0] Cr
135  * or
136  * index 1: Cr plane, [7:0] Cr
137  * index 2: Cb plane, [7:0] Cb
138  */
139 #define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */
140 #define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */
141 #define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */
142 #define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */
143 #define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */
144 #define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */
145 #define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */
146 #define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */
147 #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */
148 #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */
149 
150 /*
151  * Format Modifiers:
152  *
153  * Format modifiers describe, typically, a re-ordering or modification
154  * of the data in a plane of an FB. This can be used to express tiled/
155  * swizzled formats, or compression, or a combination of the two.
156  *
157  * The upper 8 bits of the format modifier are a vendor-id as assigned
158  * below. The lower 56 bits are assigned as vendor sees fit.
159  */
160 
161 /* Vendor Ids: */
162 #define DRM_FORMAT_MOD_NONE 0
163 #define DRM_FORMAT_MOD_VENDOR_NONE 0
164 #define DRM_FORMAT_MOD_VENDOR_INTEL 0x01
165 #define DRM_FORMAT_MOD_VENDOR_AMD 0x02
166 #define DRM_FORMAT_MOD_VENDOR_NV 0x03
167 #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
168 #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05
169 #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
170 #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
171 /* add more to the end as needed */
172 
173 #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
174 
175 #define fourcc_mod_code(vendor, val) ((((__u64)DRM_FORMAT_MOD_VENDOR_##vendor) << 56) | (val & 0x00ffffffffffffffULL))
176 
177 /*
178  * Format Modifier tokens:
179  *
180  * When adding a new token please document the layout with a code comment,
181  * similar to the fourcc codes above. drm_fourcc.h is considered the
182  * authoritative source for all of these.
183  */
184 
185 /*
186  * Invalid Modifier
187  *
188  * This modifier can be used as a sentinel to terminate the format modifiers
189  * list, or to initialize a variable with an invalid modifier. It might also be
190  * used to report an error back to userspace for certain APIs.
191  */
192 #define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED)
193 
194 /*
195  * Linear Layout
196  *
197  * Just plain linear layout. Note that this is different from no specifying any
198  * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl),
199  * which tells the driver to also take driver-internal information into account
200  * and so might actually result in a tiled framebuffer.
201  */
202 #define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0)
203 
204 /* Intel framebuffer modifiers */
205 
206 /*
207  * Intel X-tiling layout
208  *
209  * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
210  * in row-major layout. Within the tile bytes are laid out row-major, with
211  * a platform-dependent stride. On top of that the memory can apply
212  * platform-depending swizzling of some higher address bits into bit6.
213  *
214  * This format is highly platforms specific and not useful for cross-driver
215  * sharing. It exists since on a given platform it does uniquely identify the
216  * layout in a simple way for i915-specific userspace.
217  */
218 #define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1)
219 
220 /*
221  * Intel Y-tiling layout
222  *
223  * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
224  * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
225  * chunks column-major, with a platform-dependent height. On top of that the
226  * memory can apply platform-depending swizzling of some higher address bits
227  * into bit6.
228  *
229  * This format is highly platforms specific and not useful for cross-driver
230  * sharing. It exists since on a given platform it does uniquely identify the
231  * layout in a simple way for i915-specific userspace.
232  */
233 #define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2)
234 
235 /*
236  * Intel Yf-tiling layout
237  *
238  * This is a tiled layout using 4Kb tiles in row-major layout.
239  * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
240  * are arranged in four groups (two wide, two high) with column-major layout.
241  * Each group therefore consits out of four 256 byte units, which are also laid
242  * out as 2x2 column-major.
243  * 256 byte units are made out of four 64 byte blocks of pixels, producing
244  * either a square block or a 2:1 unit.
245  * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width
246  * in pixel depends on the pixel depth.
247  */
248 #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)
249 
250 /*
251  * Intel color control surface (CCS) for render compression
252  *
253  * The framebuffer format must be one of the 8:8:8:8 RGB formats.
254  * The main surface will be plane index 0 and must be Y/Yf-tiled,
255  * the CCS will be plane index 1.
256  *
257  * Each CCS tile matches a 1024x512 pixel area of the main surface.
258  * To match certain aspects of the 3D hardware the CCS is
259  * considered to be made up of normal 128Bx32 Y tiles, Thus
260  * the CCS pitch must be specified in multiples of 128 bytes.
261  *
262  * In reality the CCS tile appears to be a 64Bx64 Y tile, composed
263  * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks.
264  * But that fact is not relevant unless the memory is accessed
265  * directly.
266  */
267 #define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)
268 #define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5)
269 
270 /*
271  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
272  *
273  * Macroblocks are laid in a Z-shape, and each pixel data is following the
274  * standard NV12 style.
275  * As for NV12, an image is the result of two frame buffers: one for Y,
276  * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer).
277  * Alignment requirements are (for each buffer):
278  * - multiple of 128 pixels for the width
279  * - multiple of 32 pixels for the height
280  *
281  * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html
282  */
283 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
284 
285 /* Vivante framebuffer modifiers */
286 
287 /*
288  * Vivante 4x4 tiling layout
289  *
290  * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
291  * layout.
292  */
293 #define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1)
294 
295 /*
296  * Vivante 64x64 super-tiling layout
297  *
298  * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
299  * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
300  * major layout.
301  *
302  * For more information: see
303  * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
304  */
305 #define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2)
306 
307 /*
308  * Vivante 4x4 tiling layout for dual-pipe
309  *
310  * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
311  * different base address. Offsets from the base addresses are therefore halved
312  * compared to the non-split tiled layout.
313  */
314 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3)
315 
316 /*
317  * Vivante 64x64 super-tiling layout for dual-pipe
318  *
319  * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
320  * starts at a different base address. Offsets from the base addresses are
321  * therefore halved compared to the non-split super-tiled layout.
322  */
323 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
324 
325 /* NVIDIA Tegra frame buffer modifiers */
326 
327 /*
328  * Some modifiers take parameters, for example the number of vertical GOBs in
329  * a block. Reserve the lower 32 bits for parameters
330  */
331 #define __fourcc_mod_tegra_mode_shift 32
332 #define fourcc_mod_tegra_code(val, params) fourcc_mod_code(NV, ((((__u64)val) << __fourcc_mod_tegra_mode_shift) | params))
333 #define fourcc_mod_tegra_mod(m) (m & ~((1ULL << __fourcc_mod_tegra_mode_shift) - 1))
334 #define fourcc_mod_tegra_param(m) (m & ((1ULL << __fourcc_mod_tegra_mode_shift) - 1))
335 
336 /*
337  * Tegra Tiled Layout, used by Tegra 2, 3 and 4.
338  *
339  * Pixels are arranged in simple tiles of 16 x 16 bytes.
340  */
341 #define NV_FORMAT_MOD_TEGRA_TILED fourcc_mod_tegra_code(1, 0)
342 
343 /*
344  * Tegra 16Bx2 Block Linear layout, used by TK1/TX1
345  *
346  * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked
347  * vertically by a power of 2 (1 to 32 GOBs) to form a block.
348  *
349  * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
350  *
351  * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically.
352  * Valid values are:
353  *
354  * 0 == ONE_GOB
355  * 1 == TWO_GOBS
356  * 2 == FOUR_GOBS
357  * 3 == EIGHT_GOBS
358  * 4 == SIXTEEN_GOBS
359  * 5 == THIRTYTWO_GOBS
360  *
361  * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
362  * in full detail.
363  */
364 #define NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(v) fourcc_mod_tegra_code(2, v)
365 
366 /*
367  * Broadcom VC4 "T" format
368  *
369  * This is the primary layout that the V3D GPU can texture from (it
370  * can't do linear). The T format has:
371  *
372  * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4
373  * pixels at 32 bit depth.
374  *
375  * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
376  * 16x16 pixels).
377  *
378  * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On
379  * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows
380  * they're (TR, BR, BL, TL), where bottom left is start of memory.
381  *
382  * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
383  * tiles) or right-to-left (odd rows of 4k tiles).
384  */
385 #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
386 
387 #if defined(__cplusplus)
388 }
389 #endif
390 
391 #endif /* DRM_FOURCC_H */
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