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ApnCamera.cpp

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00001 // ApnCamera.cpp: implementation of the CApnCamera class.
00002 //
00003 // Copyright (c) 2003, 2004 Apogee Instruments, Inc.
00005 
00006 #include "stdafx.h"
00007 
00008 #include "ApnCamera.h"
00009 #include "ApnCamTable.h"
00010 
00011 
00013 // Construction/Destruction
00015 
00016 CApnCamera::CApnCamera()
00017 {
00018     m_ApnSensorInfo = NULL;
00019 }
00020 
00021 CApnCamera::~CApnCamera()
00022 {
00023     if ( m_ApnSensorInfo != NULL )
00024     {
00025         delete m_ApnSensorInfo;
00026         m_ApnSensorInfo = NULL;
00027     }
00028     CloseDriver();
00029 }
00030 
00031 bool CApnCamera::Expose( double Duration, bool Light )
00032 {
00033     ULONG           ExpTime;
00034     unsigned short  BitsPerPixel(0);
00035     unsigned short  UnbinnedRoiX;
00036     unsigned short  UnbinnedRoiY;       
00037     unsigned short  PreRoiSkip, PostRoiSkip;
00038     unsigned short  PreRoiRows, PostRoiRows;
00039     unsigned short  PreRoiVBinning, PostRoiVBinning;
00040 
00041     unsigned short  RoiRegBuffer[12];
00042     unsigned short  RoiRegData[12];
00043 
00044     unsigned short  TotalHPixels;
00045     unsigned short  TotalVPixels;
00046 
00047 
00048     while ( read_ImagingStatus() != Apn_Status_Flushing )
00049     {
00050         Sleep( 20 );
00051     }
00052 
00053     // Validate the "Duration" parameter
00054     if ( Duration < APN_EXPOSURE_TIME_MIN )
00055         Duration = APN_EXPOSURE_TIME_MIN;
00056 
00057     // Validate the ROI params
00058     UnbinnedRoiX    = m_RoiPixelsH * m_RoiBinningH;
00059 
00060     PreRoiSkip      = m_RoiStartX;
00061 
00062     PostRoiSkip     = m_ApnSensorInfo->m_TotalColumns -
00063                       m_ApnSensorInfo->m_ClampColumns -
00064                       PreRoiSkip - 
00065                       UnbinnedRoiX;
00066 
00067     TotalHPixels = UnbinnedRoiX + PreRoiSkip + PostRoiSkip + m_ApnSensorInfo->m_ClampColumns;
00068 
00069     if ( TotalHPixels != m_ApnSensorInfo->m_TotalColumns )
00070         return false;
00071 
00072     UnbinnedRoiY    = m_RoiPixelsV * m_RoiBinningV;
00073 
00074     PreRoiRows      = m_ApnSensorInfo->m_UnderscanRows + 
00075                       m_RoiStartY;
00076     
00077     PostRoiRows     = m_ApnSensorInfo->m_TotalRows -
00078                       PreRoiRows -
00079                       UnbinnedRoiY;
00080 
00081     TotalVPixels = UnbinnedRoiY + PreRoiRows + PostRoiRows;
00082 
00083     if ( TotalVPixels != m_ApnSensorInfo->m_TotalRows )
00084         return false;
00085 
00086     // Calculate the exposure time to program to the camera
00087     ExpTime = ((unsigned long)(Duration / APN_TIMER_RESOLUTION)) + APN_TIMER_OFFSET_COUNT;
00088 
00089     Write( FPGA_REG_TIMER_LOWER, (unsigned short)(ExpTime & 0xFFFF));
00090     ExpTime = ExpTime >> 16;
00091     Write( FPGA_REG_TIMER_UPPER, (unsigned short)(ExpTime & 0xFFFF));
00092 
00093     m_pvtExposurePixelsV = m_RoiPixelsV;
00094     m_pvtExposurePixelsH = m_RoiPixelsH;
00095 
00096     if ( m_DataBits == Apn_Resolution_SixteenBit )
00097     {
00098         BitsPerPixel = 16;
00099     }
00100     else if ( m_DataBits == Apn_Resolution_TwelveBit )
00101     {
00102         BitsPerPixel = 12;
00103     }
00104 
00105     if ( PreStartExpose( BitsPerPixel ) != 0 )
00106     {
00107         return false;
00108     }
00109 
00110     // Calculate the vertical parameters
00111     PreRoiVBinning  = m_ApnSensorInfo->m_RowOffsetBinning;
00112 
00113     PostRoiVBinning = 1;
00114 
00115     // For interline CCDs, set "Fast Dump" mode if the particular array is NOT digitized
00116     if ( m_ApnSensorInfo->m_InterlineCCD )
00117     {
00118         // use the fast dump feature to get rid of the data quickly.
00119         // one row, binning to the original row count
00120         // note that we only are not digitized in arrays 1 and 3
00121         PreRoiVBinning  = PreRoiRows;
00122         PostRoiVBinning = PostRoiRows;
00123 
00124         PreRoiVBinning  |= FPGA_BIT_ARRAY_FASTDUMP;
00125         PostRoiVBinning |= FPGA_BIT_ARRAY_FASTDUMP;
00126 
00127         PreRoiRows  = 1;
00128         PostRoiRows = 1;
00129     }
00130 
00131         // Set up the geometry for a full frame device
00132         if ( m_ApnSensorInfo->m_EnableSingleRowOffset )
00133         {
00134                 PreRoiVBinning  += PreRoiRows;
00135                 PostRoiVBinning = PostRoiRows;
00136                                                                             
00137                 PreRoiVBinning  |= FPGA_BIT_ARRAY_FASTDUMP;
00138                 PostRoiVBinning |= FPGA_BIT_ARRAY_FASTDUMP;
00139                                                                             
00140                 PreRoiRows      = 1;
00141                 PostRoiRows     = 1;
00142         }
00143                                                                             
00144 
00145     // Issue the reset
00146     RoiRegBuffer[0] = FPGA_REG_COMMAND_B;
00147     RoiRegData[0]   = FPGA_BIT_CMD_RESET;
00148 
00149     // Program the horizontal settings
00150     RoiRegBuffer[1] = FPGA_REG_PREROI_SKIP_COUNT;
00151     RoiRegData[1]   = PreRoiSkip;
00152 
00153     RoiRegBuffer[2] = FPGA_REG_ROI_COUNT;
00154     // Number of ROI pixels.  Adjust the 12bit operation here to account for an extra 
00155     // 10 pixel shift as a result of the A/D conversion.
00156     if ( m_DataBits == Apn_Resolution_SixteenBit )
00157     {
00158         RoiRegData[2]   = m_pvtExposurePixelsH + 1;
00159     }
00160     else if ( m_DataBits == Apn_Resolution_TwelveBit )
00161     {
00162         RoiRegData[2]   = m_pvtExposurePixelsH + 10;
00163     }
00164 
00165     RoiRegBuffer[3] = FPGA_REG_POSTROI_SKIP_COUNT;
00166     RoiRegData[3]   = PostRoiSkip;
00167 
00168     // Program the vertical settings
00169     RoiRegBuffer[4] = FPGA_REG_A1_ROW_COUNT;
00170     RoiRegData[4]   = PreRoiRows;
00171     RoiRegBuffer[5] = FPGA_REG_A1_VBINNING;
00172     RoiRegData[5]   = PreRoiVBinning;
00173 
00174     RoiRegBuffer[6] = FPGA_REG_A2_ROW_COUNT;
00175     RoiRegData[6]   = m_RoiPixelsV;
00176     RoiRegBuffer[7] = FPGA_REG_A2_VBINNING;
00177     RoiRegData[7]   = (m_RoiBinningV | FPGA_BIT_ARRAY_DIGITIZE);
00178 
00179     RoiRegBuffer[8] = FPGA_REG_A3_ROW_COUNT;
00180     RoiRegData[8]   = PostRoiRows;
00181     RoiRegBuffer[9] = FPGA_REG_A3_VBINNING;
00182     RoiRegData[9]   = PostRoiVBinning;
00183 
00184     // Issue the reset
00185     RoiRegBuffer[10]    = FPGA_REG_COMMAND_B;
00186     RoiRegData[10]      = FPGA_BIT_CMD_RESET;
00187 
00188     switch ( m_pvtCameraMode )
00189     {
00190     case Apn_CameraMode_Normal:
00191         if ( Light )
00192         {
00193             RoiRegBuffer[11]    = FPGA_REG_COMMAND_A;
00194             RoiRegData[11]      = FPGA_BIT_CMD_EXPOSE;
00195         }
00196         else
00197         {
00198             RoiRegBuffer[11]    = FPGA_REG_COMMAND_A;
00199             RoiRegData[11]      = FPGA_BIT_CMD_DARK;
00200         }
00201         break;
00202     case Apn_CameraMode_TDI:
00203         RoiRegBuffer[11]        = FPGA_REG_COMMAND_A;
00204         RoiRegData[11]          = FPGA_BIT_CMD_TDI;
00205         break;
00206     case Apn_CameraMode_Test:
00207         if ( Light )
00208         {
00209             RoiRegBuffer[11]    = FPGA_REG_COMMAND_A;
00210             RoiRegData[11]      = FPGA_BIT_CMD_EXPOSE;
00211         }
00212         else
00213         {
00214             RoiRegBuffer[11]    = FPGA_REG_COMMAND_A;
00215             RoiRegData[11]      = FPGA_BIT_CMD_DARK;
00216         }
00217         break;
00218     case Apn_CameraMode_ExternalTrigger:
00219         RoiRegBuffer[11]        = FPGA_REG_COMMAND_A;
00220         RoiRegData[11]          = FPGA_BIT_CMD_TRIGGER_EXPOSE;
00221         break;
00222     case Apn_CameraMode_ExternalShutter:
00223         break;
00224     }
00225 
00226     // Send the instruction sequence to the camera
00227     WriteMultiMRMD( RoiRegBuffer, RoiRegData, 12 );
00228 
00229     m_pvtImageInProgress = true;
00230     m_pvtImageReady      = false;
00231 
00232     return true;
00233 }
00234 
00235 bool CApnCamera::ResetSystem()
00236 {
00237     // Reset the camera engine
00238     Write( FPGA_REG_COMMAND_B, FPGA_BIT_CMD_RESET );
00239 
00240     // Start flushing
00241     Write( FPGA_REG_COMMAND_A, FPGA_BIT_CMD_FLUSH );
00242 
00243     return true;
00244 }
00245 
00246 bool CApnCamera::PauseTimer( bool PauseState )
00247 {
00248     unsigned short RegVal;
00249     bool           CurrentState;
00250 
00251     Read( FPGA_REG_OP_A, RegVal );
00252 
00253     CurrentState = ( RegVal & FPGA_BIT_PAUSE_TIMER ) == FPGA_BIT_PAUSE_TIMER;
00254 
00255     if ( CurrentState != PauseState )
00256     {
00257         if ( PauseState )
00258         {
00259             RegVal |= FPGA_BIT_PAUSE_TIMER;
00260         }
00261         else
00262         {
00263             RegVal &= ~FPGA_BIT_PAUSE_TIMER;
00264         }
00265         Write ( FPGA_REG_OP_A, RegVal );
00266     }
00267 
00268     return true;
00269 }
00270 
00271 bool CApnCamera::StopExposure( bool DigitizeData )
00272 {
00273     if ( m_pvtImageInProgress )
00274     {
00275         Write( FPGA_REG_COMMAND_B, FPGA_BIT_CMD_END_EXPOSURE );
00276 
00277         if ( PostStopExposure( DigitizeData ) != 0 )
00278         {
00279             return false;
00280         }
00281     }
00282 
00283     return true;
00284 }
00285                                                                            
00286 
00287 unsigned short CApnCamera::GetExposurePixelsH()
00288 {
00289     return m_pvtExposurePixelsH;
00290 }
00291 
00292 unsigned short CApnCamera::GetExposurePixelsV()
00293 {
00294     return m_pvtExposurePixelsV;
00295 }
00296 
00297 double CApnCamera::read_InputVoltage()
00298 {
00299     UpdateGeneralStatus();
00300 
00301     return m_pvtInputVoltage;
00302 }
00303 
00304 long CApnCamera::read_AvailableMemory()
00305 {
00306         long AvailableMemory(0);
00307 
00308     switch( m_CameraInterface )
00309     {
00310     case Apn_Interface_NET:
00311         AvailableMemory = 28 * 1024;
00312         break;
00313     case Apn_Interface_USB:
00314         AvailableMemory = 32 * 1024;
00315         break;
00316     default:
00317         break;
00318     }
00319 
00320     return AvailableMemory;
00321 }
00322 
00323 unsigned short CApnCamera::read_FirmwareVersion()
00324 {
00325     unsigned short FirmwareVersion;
00326     Read( FPGA_REG_FIRMWARE_REV, FirmwareVersion );
00327     return FirmwareVersion;
00328 }
00329 
00330 bool CApnCamera::read_ShutterState()
00331 {
00332     UpdateGeneralStatus();
00333 
00334     return m_pvtShutterState;
00335 }
00336 
00337 bool CApnCamera::read_DisableShutter()
00338 {
00339     unsigned short RegVal;
00340     Read( FPGA_REG_OP_A, RegVal );
00341     return ( (RegVal & FPGA_BIT_DISABLE_SHUTTER) != 0 );
00342 }
00343 
00344 void CApnCamera::write_DisableShutter( bool DisableShutter )
00345 {
00346     unsigned short RegVal;
00347     Read( FPGA_REG_OP_A, RegVal );
00348 
00349     if ( DisableShutter )
00350         RegVal |= FPGA_BIT_DISABLE_SHUTTER;
00351     else
00352         RegVal &= ~FPGA_BIT_DISABLE_SHUTTER;
00353 
00354     Write( FPGA_REG_OP_A, RegVal );
00355 }
00356 
00357 bool CApnCamera::read_ForceShutterOpen()
00358 {
00359     unsigned short RegVal;
00360     Read( FPGA_REG_OP_A, RegVal );
00361     return ( (RegVal & FPGA_BIT_FORCE_SHUTTER) != 0 );
00362 }
00363 
00364 void CApnCamera::write_ForceShutterOpen( bool ForceShutterOpen )
00365 {
00366     unsigned short RegVal;
00367     Read( FPGA_REG_OP_A, RegVal );
00368     
00369     if ( ForceShutterOpen )
00370         RegVal |= FPGA_BIT_FORCE_SHUTTER;
00371     else 
00372         RegVal &= ~FPGA_BIT_FORCE_SHUTTER;
00373 
00374     Write( FPGA_REG_OP_A, RegVal );
00375 }
00376 
00377 bool CApnCamera::read_ShutterAmpControl()
00378 {
00379     unsigned short RegVal;
00380     Read( FPGA_REG_OP_A, RegVal );
00381     return ( (RegVal & FPGA_BIT_SHUTTER_AMP_CONTROL ) != 0 );
00382 }
00383 
00384 void CApnCamera::write_ShutterAmpControl( bool ShutterAmpControl )
00385 {
00386     unsigned short RegVal;
00387     Read( FPGA_REG_OP_A, RegVal );
00388 
00389     if ( ShutterAmpControl )
00390         RegVal |= FPGA_BIT_SHUTTER_AMP_CONTROL;
00391     else
00392         RegVal &= ~FPGA_BIT_SHUTTER_AMP_CONTROL;
00393 
00394     Write( FPGA_REG_OP_A, RegVal );
00395 }
00396 
00397 bool CApnCamera::read_ExternalIoReadout()
00398 {
00399     unsigned short  RegVal;
00400     Read( FPGA_REG_OP_A, RegVal );
00401     return ( (RegVal & FPGA_BIT_SHUTTER_MODE) != 0 );
00402 }
00403 
00404 void CApnCamera::write_ExternalIoReadout( bool ExternalIoReadout )
00405 {
00406     unsigned short  RegVal;
00407     Read( FPGA_REG_OP_A, RegVal );
00408 
00409     if ( ExternalIoReadout )
00410         RegVal |= FPGA_BIT_SHUTTER_MODE;
00411     else
00412         RegVal &= ~FPGA_BIT_SHUTTER_MODE;
00413 
00414     Write( FPGA_REG_OP_A, RegVal );
00415 }
00416 
00417 bool CApnCamera::read_FastSequence()
00418 {
00419     if ( m_ApnSensorInfo->m_InterlineCCD == false )
00420         return false;
00421 
00422     unsigned short  RegVal;
00423     Read( FPGA_REG_OP_A, RegVal );
00424     return ( (RegVal & FPGA_BIT_RATIO) != 0 );
00425 }
00426 
00427 void CApnCamera::write_FastSequence( bool FastSequence )
00428 {
00429     if ( m_ApnSensorInfo->m_InterlineCCD == false )
00430         return;
00431 
00432     unsigned short  RegVal;
00433     Read( FPGA_REG_OP_A, RegVal );
00434 
00435     if ( FastSequence )
00436     {
00437         RegVal |= FPGA_BIT_RATIO;
00438         Write( FPGA_REG_SHUTTER_CLOSE_DELAY, 0x0 );
00439     }
00440     else
00441     {
00442         RegVal &= ~FPGA_BIT_RATIO;
00443     }
00444 
00445     Write( FPGA_REG_OP_A, RegVal );
00446 }
00447 
00448 Apn_NetworkMode CApnCamera::read_NetworkTransferMode()
00449 {
00450     return m_pvtNetworkTransferMode;
00451 }
00452 
00453 void CApnCamera::write_NetworkTransferMode( Apn_NetworkMode TransferMode )
00454 {
00455     SetNetworkTransferMode( TransferMode );
00456 
00457     m_pvtNetworkTransferMode = TransferMode;
00458 }
00459 
00460 Apn_CameraMode CApnCamera::read_CameraMode()
00461 {
00462     return m_pvtCameraMode;
00463 }
00464 
00465 void CApnCamera::write_CameraMode( Apn_CameraMode CameraMode )
00466 {
00467     unsigned short RegVal;
00468 
00469 
00470     // If our state isn't going to change, do nothing
00471     if ( m_pvtCameraMode == CameraMode )
00472         return;
00473 
00474     // If we didn't return already, then if we know our state is going to
00475     // change.  If we're in test mode, clear the appropriate FPGA bit(s).
00476     switch( m_pvtCameraMode )
00477     {
00478     case Apn_CameraMode_Normal:
00479         break;
00480     case Apn_CameraMode_TDI:
00481         break;
00482     case Apn_CameraMode_Test:
00483         Read( FPGA_REG_OP_B, RegVal );
00484         RegVal &= ~FPGA_BIT_AD_SIMULATION;
00485         Write( FPGA_REG_OP_B, RegVal );
00486         break;
00487     case Apn_CameraMode_ExternalTrigger:
00488         break;
00489     case Apn_CameraMode_ExternalShutter:
00490         Read( FPGA_REG_OP_A, RegVal );
00491         RegVal &= ~FPGA_BIT_SHUTTER_SOURCE;
00492         Write( FPGA_REG_OP_A, RegVal );
00493         break;
00494     }
00495     
00496     switch ( CameraMode )
00497     {
00498     case Apn_CameraMode_Normal:
00499         break;
00500     case Apn_CameraMode_TDI:
00501         break;
00502     case Apn_CameraMode_Test:
00503         Read( FPGA_REG_OP_B, RegVal );
00504         RegVal |= FPGA_BIT_AD_SIMULATION;
00505         Write( FPGA_REG_OP_B, RegVal );
00506         break;
00507     case Apn_CameraMode_ExternalTrigger:
00508                 Read( FPGA_REG_IO_PORT_ASSIGNMENT, RegVal );
00509                 RegVal |= 0x01;
00510                 Write( FPGA_REG_IO_PORT_ASSIGNMENT, RegVal );
00511         break;
00512     case Apn_CameraMode_ExternalShutter:
00513         Read( FPGA_REG_OP_A, RegVal );
00514         RegVal |= FPGA_BIT_SHUTTER_SOURCE;
00515         Write( FPGA_REG_OP_A, RegVal );
00516         break;
00517     }
00518 
00519     m_pvtCameraMode = CameraMode;
00520 }
00521 
00522 void CApnCamera::write_DataBits( Apn_Resolution BitResolution )
00523 {
00524     unsigned short  RegVal;
00525 
00526     if ( m_CameraInterface == Apn_Interface_NET )
00527     {
00528         // The network interface is 16bpp only.  Changing the resolution 
00529         // for network cameras has no effect.
00530         return;
00531     }
00532 
00533     if ( m_DataBits != BitResolution )
00534     {
00535         // Reset the camera
00536         Write( FPGA_REG_COMMAND_B, FPGA_BIT_CMD_RESET );
00537 
00538         // Change bit setting after the reset
00539         Read( FPGA_REG_OP_A, RegVal );
00540         
00541         if ( BitResolution == Apn_Resolution_TwelveBit )
00542             RegVal |= FPGA_BIT_DIGITIZATION_RES;
00543 
00544         if ( BitResolution == Apn_Resolution_SixteenBit )
00545             RegVal &= ~FPGA_BIT_DIGITIZATION_RES;
00546 
00547         Write( FPGA_REG_OP_A, RegVal );
00548 
00549         m_DataBits = BitResolution;
00550         
00551         LoadClampPattern();
00552         LoadSkipPattern();
00553         LoadRoiPattern( m_RoiBinningH );
00554 
00555         // Reset the camera
00556         Write( FPGA_REG_COMMAND_B, FPGA_BIT_CMD_RESET );
00557         // Start flushing
00558         Write( FPGA_REG_COMMAND_A, FPGA_BIT_CMD_FLUSH );
00559     }
00560 }
00561 
00562 Apn_Status CApnCamera::read_ImagingStatus()
00563 {
00564     bool Exposing, Active, Done, Flushing, WaitOnTrigger;
00565     bool DataHalted, RamError;
00566 
00567 
00568     UpdateGeneralStatus();
00569 
00570     // Update the ImagingStatus
00571     Exposing        = false;
00572     Active          = false;
00573     Done            = false;
00574     Flushing        = false;
00575     WaitOnTrigger   = false;
00576     DataHalted      = false;
00577     RamError        = false;
00578 
00579     if ( (m_pvtStatusReg & FPGA_BIT_STATUS_IMAGING_ACTIVE) != 0 )
00580         Active = true;
00581     
00582     if ( (m_pvtStatusReg & FPGA_BIT_STATUS_IMAGE_EXPOSING) != 0 )
00583         Exposing = true;
00584     
00585     if ( (m_pvtStatusReg & FPGA_BIT_STATUS_IMAGE_DONE) != 0 )
00586         Done = true;
00587     
00588     if ( (m_pvtStatusReg & FPGA_BIT_STATUS_FLUSHING) != 0 )
00589         Flushing = true;
00590     
00591     if ( (m_pvtStatusReg & FPGA_BIT_STATUS_WAITING_TRIGGER) != 0 )
00592         WaitOnTrigger = true;
00593 
00594     if ( (m_pvtStatusReg & FPGA_BIT_STATUS_DATA_HALTED) != 0 )
00595         DataHalted = true;
00596 
00597     if ( (m_pvtStatusReg & FPGA_BIT_STATUS_PATTERN_ERROR) != 0 )
00598         RamError = true;
00599 
00600     if ( RamError )
00601     {
00602         m_pvtImagingStatus = Apn_Status_PatternError;
00603     }
00604     else
00605     {
00606         if ( DataHalted )
00607         {
00608             m_pvtImagingStatus = Apn_Status_DataError;
00609         }
00610         else
00611         {
00612             if ( WaitOnTrigger )
00613             {
00614                 m_pvtImagingStatus = Apn_Status_WaitingOnTrigger;
00615             }
00616             else
00617             {
00618                 if ( Done && m_pvtImageInProgress )
00619                 {
00620                     m_pvtImageReady         = true;
00621                     m_pvtImagingStatus      = Apn_Status_ImageReady;
00622                 }
00623                 else
00624                 {
00625                     if ( Active )
00626                     {
00627                         if ( Exposing )
00628                             m_pvtImagingStatus = Apn_Status_Exposing;
00629                         else
00630                             m_pvtImagingStatus = Apn_Status_ImagingActive;
00631                     }
00632                     else
00633                     {
00634                         if ( Flushing )
00635                             m_pvtImagingStatus = Apn_Status_Flushing;
00636                         else
00637                             m_pvtImagingStatus = Apn_Status_Idle;
00638                     }
00639                 }
00640             }
00641         }
00642     }
00643 
00644     /*
00645     switch( m_pvtImagingStatus )
00646     {
00647     case Apn_Status_DataError:
00648         OutputDebugString( "ImagingStatus: Apn_Status_DataError" );
00649         break;
00650     case Apn_Status_PatternError:
00651         OutputDebugString( "ImagingStatus: Apn_Status_PatternError" );
00652         break;
00653     case Apn_Status_Idle:
00654         OutputDebugString( "ImagingStatus: Apn_Status_Idle" );
00655         break;
00656     case Apn_Status_Exposing:
00657         OutputDebugString( "ImagingStatus: Apn_Status_Exposing" );
00658         break;
00659     case Apn_Status_ImagingActive:
00660         OutputDebugString( "ImagingStatus: Apn_Status_ImagingActive" );
00661         break;
00662         case Apn_Status_ImageReady:
00663                 OutputDebugString( "ImagingStatus: Apn_Status_ImageReady" );
00664                 break;
00665     case Apn_Status_Flushing:
00666         OutputDebugString( "ImagingStatus: Apn_Status_Flushing" );
00667         break;
00668     case Apn_Status_WaitingOnTrigger:
00669         OutputDebugString( "ImagingStatus: Apn_Status_WaitingOnTrigger" );
00670         break;
00671     default:
00672         OutputDebugString( "ImagingStatus: UNDEFINED!!" );
00673         break;
00674     }
00675     */
00676 
00677     return m_pvtImagingStatus;
00678 }
00679 
00680 Apn_LedMode CApnCamera::read_LedMode()
00681 {
00682     return m_pvtLedMode;
00683 }
00684 
00685 void CApnCamera::write_LedMode( Apn_LedMode LedMode )
00686 {
00687     unsigned short  RegVal;
00688 
00689     Read( FPGA_REG_OP_A, RegVal );
00690 
00691     switch ( LedMode )
00692     {
00693     case Apn_LedMode_DisableAll:
00694         RegVal |= FPGA_BIT_LED_DISABLE;
00695         break;
00696     case Apn_LedMode_DisableWhileExpose:
00697         RegVal &= ~FPGA_BIT_LED_DISABLE;
00698         RegVal |= FPGA_BIT_LED_EXPOSE_DISABLE;
00699         break;
00700     case Apn_LedMode_EnableAll:
00701         RegVal &= ~FPGA_BIT_LED_DISABLE;
00702         RegVal &= ~FPGA_BIT_LED_EXPOSE_DISABLE;
00703         break;
00704     }
00705 
00706     m_pvtLedMode = LedMode;
00707 
00708     Write( FPGA_REG_OP_A, RegVal );
00709 }
00710 
00711 Apn_LedState CApnCamera::read_LedState( unsigned short LedId )
00712 {
00713         Apn_LedState RetVal(0);
00714 
00715     if ( LedId == 0 )               // LED A
00716         RetVal = m_pvtLedStateA;
00717     
00718     if ( LedId == 1 )               // LED B
00719         RetVal = m_pvtLedStateB;
00720 
00721     return RetVal;
00722 }
00723 
00724 void CApnCamera::write_LedState( unsigned short LedId, Apn_LedState LedState )
00725 {
00726     unsigned short  RegVal;
00727 
00728 
00729     RegVal = 0x0;
00730 
00731     if ( LedId == 0 )           // LED A
00732     {
00733         RegVal = (m_pvtLedStateB << 4); // keep the current settings for LED B
00734         RegVal |= LedState;             // program new settings
00735         m_pvtLedStateA = LedState;
00736     }
00737     else if ( LedId == 1 )      // LED B
00738     {
00739         RegVal = m_pvtLedStateA;        // keep the current settings for LED A
00740         RegVal |= (LedState << 4);      // program new settings
00741         m_pvtLedStateB = LedState;
00742     }
00743 
00744     Write( FPGA_REG_LED_SELECT, RegVal );
00745 }
00746 
00747 bool CApnCamera::read_CoolerEnable()
00748 {
00749     return m_pvtCoolerEnable;
00750 }
00751 
00752 void CApnCamera::write_CoolerEnable( bool CoolerEnable )
00753 {
00754     if ( CoolerEnable )
00755     {
00756         Write( FPGA_REG_COMMAND_B, FPGA_BIT_CMD_RAMP_TO_SETPOINT );
00757     }
00758     else
00759     {
00760         Write( FPGA_REG_COMMAND_B, FPGA_BIT_CMD_RAMP_TO_AMBIENT );
00761     }
00762 
00763     m_pvtCoolerEnable = CoolerEnable;
00764 }
00765 
00766 Apn_CoolerStatus CApnCamera::read_CoolerStatus()
00767 {
00768     bool CoolerAtTemp;
00769     bool CoolerActive;
00770     bool CoolerTempRevised;
00771 
00772 
00773     UpdateGeneralStatus();
00774 
00775     // Update CoolerStatus
00776     CoolerActive        = false;
00777     CoolerAtTemp        = false;
00778     CoolerTempRevised   = false;
00779 
00780     if ( (m_pvtStatusReg & FPGA_BIT_STATUS_TEMP_AT_TEMP) != 0 )
00781         CoolerAtTemp = true;
00782     
00783     if ( (m_pvtStatusReg & FPGA_BIT_STATUS_TEMP_ACTIVE) != 0 )
00784         CoolerActive = true;
00785 
00786     if ( (m_pvtStatusReg & FPGA_BIT_STATUS_TEMP_REVISION) != 0 )
00787         CoolerTempRevised = true;
00788 
00789     // Now derive our cooler state
00790     if ( !CoolerActive )
00791     {
00792         m_pvtCoolerStatus = Apn_CoolerStatus_Off;
00793     }
00794     else
00795     {
00796         if ( CoolerTempRevised )
00797         {
00798             m_pvtCoolerStatus = Apn_CoolerStatus_Revision;
00799         }
00800         else
00801         {
00802             if ( CoolerAtTemp )
00803                 m_pvtCoolerStatus = Apn_CoolerStatus_AtSetPoint;
00804             else
00805                 m_pvtCoolerStatus = Apn_CoolerStatus_RampingToSetPoint;
00806 
00807         }
00808     }
00809 
00810     return m_pvtCoolerStatus;
00811 }
00812 
00813 double CApnCamera::read_CoolerSetPoint()
00814 {
00815     unsigned short  RegVal;
00816     double          TempVal;
00817 
00818     Read( FPGA_REG_TEMP_DESIRED, RegVal );
00819     
00820     RegVal &= 0x0FFF;
00821 
00822     TempVal = ( RegVal - APN_TEMP_SETPOINT_ZERO_POINT ) * APN_TEMP_DEGREES_PER_BIT;
00823 
00824     return TempVal;
00825 }
00826 
00827 void CApnCamera::write_CoolerSetPoint( double SetPoint )
00828 {
00829     unsigned short  RegVal;
00830     double          TempVal;
00831     
00832 
00833     TempVal = SetPoint;
00834 
00835     if ( SetPoint < (APN_TEMP_SETPOINT_MIN - APN_TEMP_KELVIN_SCALE_OFFSET) )
00836         TempVal = APN_TEMP_SETPOINT_MIN;
00837 
00838     if ( SetPoint > (APN_TEMP_SETPOINT_MAX - APN_TEMP_KELVIN_SCALE_OFFSET) )
00839         TempVal = APN_TEMP_SETPOINT_MAX;
00840 
00841     RegVal = (unsigned short)( (TempVal / APN_TEMP_DEGREES_PER_BIT) + APN_TEMP_SETPOINT_ZERO_POINT );
00842     
00843     Write( FPGA_REG_TEMP_DESIRED, RegVal );
00844 }
00845 
00846 double CApnCamera::read_CoolerBackoffPoint()
00847 {
00848     return ( m_pvtCoolerBackoffPoint );
00849 }
00850 
00851 void CApnCamera::write_CoolerBackoffPoint( double BackoffPoint )
00852 {
00853     unsigned short  RegVal;
00854     double          TempVal;
00855     
00856     TempVal = BackoffPoint;
00857 
00858     // BackoffPoint must be a positive number!
00859     if ( BackoffPoint < 0.0 )
00860         TempVal = 0.0;
00861 
00862     if ( BackoffPoint < (APN_TEMP_SETPOINT_MIN - APN_TEMP_KELVIN_SCALE_OFFSET) )
00863         TempVal = APN_TEMP_SETPOINT_MIN;
00864 
00865     if ( BackoffPoint > (APN_TEMP_SETPOINT_MAX - APN_TEMP_KELVIN_SCALE_OFFSET) )
00866         TempVal = APN_TEMP_SETPOINT_MAX;
00867 
00868     m_pvtCoolerBackoffPoint = TempVal;
00869 
00870     RegVal = (unsigned short)( TempVal / APN_TEMP_DEGREES_PER_BIT );
00871     
00872     Write( FPGA_REG_TEMP_BACKOFF, RegVal );
00873 }
00874 
00875 double CApnCamera::read_CoolerDrive()
00876 {
00877     UpdateGeneralStatus();
00878 
00879     return m_pvtCoolerDrive;
00880 }
00881 
00882 double CApnCamera::read_TempCCD()
00883 {
00884     // UpdateGeneralStatus();
00885 
00886     unsigned short  TempReg;
00887     unsigned short  TempAvg;
00888     unsigned long   TempTotal;
00889         int     don;
00890 
00891     TempTotal = 0;
00892         don = 8;
00893         if ( m_CameraInterface == Apn_Interface_NET ) {
00894            don = 1;
00895         }
00896 
00897     for ( int i=0; i<don; i++ )
00898     {
00899         Read( FPGA_REG_TEMP_CCD, TempReg );
00900         TempTotal += TempReg;
00901     }
00902 
00903     TempAvg = (unsigned short)(TempTotal / don);
00904 
00905     m_pvtCurrentCcdTemp = ( (TempAvg - APN_TEMP_SETPOINT_ZERO_POINT) 
00906                                     * APN_TEMP_DEGREES_PER_BIT );
00907 
00908     return m_pvtCurrentCcdTemp;
00909 }
00910 
00911 double CApnCamera::read_TempHeatsink()
00912 {
00913     // UpdateGeneralStatus();
00914 
00915     unsigned short  TempReg;
00916     unsigned short  TempAvg;
00917     unsigned long   TempTotal;
00918         int don;
00919 
00920     TempTotal = 0;
00921         don = 8;
00922         if ( m_CameraInterface == Apn_Interface_NET ) {
00923            don = 1;
00924         }
00925 
00926     for ( int i=0; i<don; i++ )
00927     {
00928         Read( FPGA_REG_TEMP_HEATSINK, TempReg );
00929         TempTotal += TempReg;
00930     }
00931 
00932     TempAvg = (unsigned short)(TempTotal / don);
00933 
00934     m_pvtCurrentHeatsinkTemp = ( (TempAvg - APN_TEMP_HEATSINK_ZERO_POINT) 
00935                                     * APN_TEMP_DEGREES_PER_BIT );
00936 
00937     return m_pvtCurrentHeatsinkTemp;
00938 }
00939 
00940 Apn_FanMode CApnCamera::read_FanMode()
00941 {
00942     return m_pvtFanMode;
00943 }
00944 
00945 void CApnCamera::write_FanMode( Apn_FanMode FanMode )
00946 {
00947     unsigned short  RegVal;
00948     unsigned short  OpRegA;
00949 
00950 
00951     if ( m_pvtFanMode == FanMode )
00952         return;
00953 
00954     if ( m_pvtCoolerEnable )
00955     {
00956         Read( FPGA_REG_OP_A, OpRegA );
00957         OpRegA |= FPGA_BIT_TEMP_SUSPEND;
00958         Write( FPGA_REG_OP_A, OpRegA );
00959 
00960         do 
00961         { 
00962             Read( FPGA_REG_GENERAL_STATUS, RegVal );
00963         } while ( (RegVal & FPGA_BIT_STATUS_TEMP_SUSPEND_ACK) == 0 );
00964         
00965     }
00966 
00967     switch ( FanMode )
00968     {
00969     case Apn_FanMode_Off:
00970         RegVal = APN_FAN_SPEED_OFF;
00971         break;
00972     case Apn_FanMode_Low:
00973         RegVal = APN_FAN_SPEED_LOW;
00974         break;
00975     case Apn_FanMode_Medium:
00976         RegVal = APN_FAN_SPEED_MEDIUM;
00977         break;
00978     case Apn_FanMode_High:
00979         RegVal = APN_FAN_SPEED_HIGH;
00980         break;
00981     }
00982 
00983     Write( FPGA_REG_FAN_SPEED_CONTROL, RegVal );
00984 
00985     Read( FPGA_REG_OP_B, RegVal );
00986     RegVal |= FPGA_BIT_DAC_SELECT_ZERO;
00987     RegVal &= ~FPGA_BIT_DAC_SELECT_ONE;
00988     Write( FPGA_REG_OP_B, RegVal );
00989 
00990     Write( FPGA_REG_COMMAND_B, FPGA_BIT_CMD_DAC_LOAD );
00991 
00992     m_pvtFanMode = FanMode;
00993 
00994     if ( m_pvtCoolerEnable )
00995     {
00996         OpRegA &= ~FPGA_BIT_TEMP_SUSPEND;
00997         Write( FPGA_REG_OP_A, OpRegA );
00998     }
00999 }
01000 
01001 double CApnCamera::read_ShutterStrobePosition()
01002 {
01003     return m_pvtShutterStrobePosition;
01004 }
01005 
01006 void CApnCamera::write_ShutterStrobePosition( double Position )
01007 {
01008     unsigned short RegVal;
01009     
01010     if ( Position < APN_STROBE_POSITION_MIN )
01011         Position = APN_STROBE_POSITION_MIN;
01012 
01013     RegVal = (unsigned short)((Position - APN_STROBE_POSITION_MIN) / APN_TIMER_RESOLUTION);
01014 
01015     Write( FPGA_REG_SHUTTER_STROBE_POSITION, RegVal );
01016 
01017     m_pvtShutterStrobePosition = Position;
01018 }
01019 
01020 double CApnCamera::read_ShutterStrobePeriod()
01021 {
01022     return m_pvtShutterStrobePeriod;
01023 }
01024 
01025 void CApnCamera::write_ShutterStrobePeriod( double Period )
01026 {
01027     unsigned short RegVal;
01028 
01029     if ( Period < APN_STROBE_PERIOD_MIN )
01030         Period = APN_STROBE_PERIOD_MIN;
01031 
01032     RegVal = (unsigned short)((Period - APN_STROBE_PERIOD_MIN) / APN_PERIOD_TIMER_RESOLUTION);
01033 
01034     Write( FPGA_REG_SHUTTER_STROBE_PERIOD, RegVal );
01035     
01036     m_pvtShutterStrobePeriod = Period;
01037 }
01038 
01039 double CApnCamera::read_SequenceDelay()
01040 {
01041     return m_pvtSequenceDelay;
01042 }
01043 
01044 void CApnCamera::write_SequenceDelay( double Delay )
01045 {
01046     unsigned short RegVal;
01047 
01048     if ( Delay > APN_SEQUENCE_DELAY_LIMIT )
01049         Delay = APN_SEQUENCE_DELAY_LIMIT;
01050 
01051     m_pvtSequenceDelay = Delay;
01052 
01053     RegVal = (unsigned short)(Delay / APN_SEQUENCE_DELAY_RESOLUTION);
01054 
01055     Write( FPGA_REG_SEQUENCE_DELAY, RegVal );
01056 }
01057 
01058 bool CApnCamera::read_VariableSequenceDelay()
01059 {
01060     unsigned short RegVal;
01061     Read( FPGA_REG_OP_A, RegVal );
01062     // variable delay occurs when the bit is 0
01063     return ( (RegVal & FPGA_BIT_DELAY_MODE) == 0 ); 
01064 }
01065 
01066 void CApnCamera::write_VariableSequenceDelay( bool VariableSequenceDelay )
01067 {
01068     unsigned short RegVal;
01069 
01070     Read( FPGA_REG_OP_A, RegVal );
01071 
01072     if ( VariableSequenceDelay )
01073         RegVal &= ~FPGA_BIT_DELAY_MODE;     // variable when zero
01074     else
01075         RegVal |= FPGA_BIT_DELAY_MODE;      // constant when one
01076 
01077     Write( FPGA_REG_OP_A, RegVal );
01078 }
01079 
01080 unsigned short CApnCamera::read_ImageCount()
01081 {
01082     return m_pvtImageCount;
01083 }
01084 
01085 void CApnCamera::write_ImageCount( unsigned short Count )
01086 {
01087     if ( Count == 0 )
01088         Count = 1;
01089 
01090     Write( FPGA_REG_IMAGE_COUNT, Count );
01091     
01092     m_pvtImageCount = Count;
01093 }
01094 
01095 void CApnCamera::write_RoiBinningH( unsigned short BinningH )
01096 {
01097     // Check to see if we actually need to update the binning
01098     if ( BinningH != m_RoiBinningH )
01099     {
01100         // Reset the camera
01101         Write( FPGA_REG_COMMAND_B, FPGA_BIT_CMD_RESET );
01102 
01103         LoadRoiPattern( BinningH );
01104         m_RoiBinningH = BinningH;
01105 
01106         // Reset the camera
01107         Write( FPGA_REG_COMMAND_B, FPGA_BIT_CMD_RESET );
01108 
01109         // Start flushing
01110         Write( FPGA_REG_COMMAND_A, FPGA_BIT_CMD_FLUSH );
01111     }
01112 }
01113 
01114 void CApnCamera::write_RoiBinningV( unsigned short BinningV )
01115 {
01116     // Check to see if we actually need to update the binning
01117     if ( BinningV != m_RoiBinningV )
01118     {
01119         m_RoiBinningV = BinningV;
01120     }
01121 }
01122 
01123 void CApnCamera::write_RoiPixelsV( unsigned short PixelsV )
01124 {
01125     m_RoiPixelsV = PixelsV;
01126 }
01127 
01128 void CApnCamera::write_RoiStartY( unsigned short StartY )
01129 {
01130     m_RoiStartY = StartY;
01131 }
01132 
01133 unsigned short CApnCamera::read_OverscanColumns()
01134 {
01135     return m_ApnSensorInfo->m_OverscanColumns;
01136 }
01137 
01138 unsigned short CApnCamera::read_MaxBinningV()
01139 {
01140         if ( m_ApnSensorInfo->m_ImagingRows < APN_VBINNING_MAX )
01141                 return m_ApnSensorInfo->m_ImagingRows;
01142         else
01143                 return APN_VBINNING_MAX;
01144 }
01145 
01146 unsigned short CApnCamera::read_SequenceCounter()
01147 {
01148     unsigned short RegVal;
01149     Read( FPGA_REG_SEQUENCE_COUNTER, RegVal );
01150     return RegVal;
01151 }
01152 
01153 unsigned short CApnCamera::read_TDICounter()
01154 {
01155     unsigned short RegVal;
01156     Read( FPGA_REG_TDI_COUNTER, RegVal );
01157     return RegVal;
01158 }
01159 
01160 unsigned short CApnCamera::read_TDIRows()
01161 {
01162     return m_pvtTDIRows;
01163 }
01164 
01165 void CApnCamera::write_TDIRows( unsigned short TdiRows )
01166 {
01167     if ( TdiRows == 0 )     // Make sure the TDI row count is at least 1
01168         TdiRows = 1;
01169 
01170     Write( FPGA_REG_TDI_COUNT, TdiRows );
01171     m_pvtTDIRows = TdiRows;
01172 }
01173 
01174 double CApnCamera::read_TDIRate()
01175 {
01176     return m_pvtTDIRate;
01177 }
01178 
01179 void CApnCamera::write_TDIRate( double TdiRate )
01180 {
01181     unsigned short RegVal;
01182 
01183     if ( TdiRate < APN_TDI_RATE_MIN )
01184         TdiRate = APN_TDI_RATE_MIN;
01185     
01186     if ( TdiRate > APN_TDI_RATE_MAX )
01187         TdiRate = APN_TDI_RATE_MAX;
01188 
01189     RegVal = (unsigned short)( TdiRate / APN_TDI_RATE_RESOLUTION );
01190 
01191     Write( FPGA_REG_TDI_RATE, RegVal );
01192 
01193     m_pvtTDIRate = TdiRate;
01194 }
01195 
01196 unsigned short CApnCamera::read_IoPortAssignment()
01197 {
01198     unsigned short RegVal;
01199     Read( FPGA_REG_IO_PORT_ASSIGNMENT, RegVal );
01200     RegVal &= FPGA_MASK_IO_PORT_ASSIGNMENT;
01201     return RegVal;
01202 }
01203 
01204 void CApnCamera::write_IoPortAssignment( unsigned short IoPortAssignment )
01205 {
01206     IoPortAssignment &= FPGA_MASK_IO_PORT_ASSIGNMENT;
01207     Write( FPGA_REG_IO_PORT_ASSIGNMENT, IoPortAssignment );
01208 }
01209 
01210 unsigned short CApnCamera::read_IoPortDirection()
01211 {
01212     unsigned short RegVal;
01213     Read( FPGA_REG_IO_PORT_DIRECTION, RegVal );
01214     RegVal &= FPGA_MASK_IO_PORT_DIRECTION;
01215     return RegVal;
01216 }
01217 
01218 void CApnCamera::write_IoPortDirection( unsigned short IoPortDirection )
01219 {
01220     IoPortDirection &= FPGA_MASK_IO_PORT_DIRECTION;
01221     Write( FPGA_REG_IO_PORT_DIRECTION, IoPortDirection );
01222 }
01223 
01224 unsigned short CApnCamera::read_IoPortData()
01225 {
01226     unsigned short RegVal;
01227     Read( FPGA_REG_IO_PORT_READ, RegVal );
01228     RegVal &= FPGA_MASK_IO_PORT_DATA;
01229     return RegVal;
01230 }
01231 
01232 void CApnCamera::write_IoPortData( unsigned short IoPortData )
01233 {
01234     IoPortData &= FPGA_MASK_IO_PORT_DATA;
01235     Write( FPGA_REG_IO_PORT_WRITE, IoPortData );
01236 }
01237 
01238 unsigned short CApnCamera::read_TwelveBitGain()
01239 {
01240     return m_pvtTwelveBitGain;
01241 }
01242 
01243 void CApnCamera::write_TwelveBitGain( unsigned short TwelveBitGain )
01244 {
01245     unsigned short NewVal;
01246     unsigned short StartVal;
01247     unsigned short FirstBit;
01248 
01249     NewVal      = 0x0;
01250     StartVal    = TwelveBitGain & 0x3FF;
01251 
01252     for ( int i=0; i<10; i++ )
01253     {
01254         FirstBit = ( StartVal & 0x0001 );
01255         NewVal |= ( FirstBit << (10-i) );
01256         StartVal = StartVal >> 1;
01257     }
01258 
01259     NewVal |= 0x4000;
01260 
01261     Write( FPGA_REG_AD_CONFIG_DATA, NewVal );
01262     Write( FPGA_REG_COMMAND_B,      0x8000 );
01263 
01264     m_pvtTwelveBitGain = TwelveBitGain & 0x3FF;
01265 }
01266 
01267 double CApnCamera::read_MaxExposureTime()
01268 {
01269     return APN_EXPOSURE_TIME_MAX;
01270 }
01271 
01272 double CApnCamera::read_TestLedBrightness()
01273 {
01274     return m_pvtTestLedBrightness;
01275 }
01276 
01277 void CApnCamera::write_TestLedBrightness( double TestLedBrightness )
01278 {
01279     unsigned short  RegVal;
01280     unsigned short  OpRegA;
01281 
01282 
01283     if ( TestLedBrightness == m_pvtTestLedBrightness )
01284         return;
01285 
01286     if ( m_pvtCoolerEnable )
01287     {
01288         Read( FPGA_REG_OP_A, OpRegA );
01289         OpRegA |= FPGA_BIT_TEMP_SUSPEND;
01290         Write( FPGA_REG_OP_A, OpRegA );
01291 
01292         do 
01293         { 
01294             Read( FPGA_REG_GENERAL_STATUS, RegVal );
01295         } while ( (RegVal & FPGA_BIT_STATUS_TEMP_SUSPEND_ACK) == 0 );
01296         
01297     }
01298 
01299     RegVal = (unsigned short)( (double)FPGA_MASK_LED_ILLUMINATION * (TestLedBrightness/100.0) );
01300     
01301     Write( FPGA_REG_LED_DRIVE, RegVal );
01302 
01303     Read( FPGA_REG_OP_B, RegVal );
01304     RegVal &= ~FPGA_BIT_DAC_SELECT_ZERO;
01305     RegVal |= FPGA_BIT_DAC_SELECT_ONE;
01306     Write( FPGA_REG_OP_B, RegVal );
01307 
01308     Write( FPGA_REG_COMMAND_B, FPGA_BIT_CMD_DAC_LOAD );
01309 
01310     m_pvtTestLedBrightness = TestLedBrightness;
01311 
01312     if ( m_pvtCoolerEnable )
01313     {
01314         OpRegA &= ~FPGA_BIT_TEMP_SUSPEND;
01315         Write( FPGA_REG_OP_A, OpRegA );
01316     }
01317 }
01318 
01319 
01320 
01321 
01322 
01323 
01324 
01325 
01326 long CApnCamera::LoadVerticalPattern()
01327 {
01328     unsigned short RegData;
01329 
01330     // Prime the RAM (Enable)
01331     Read( FPGA_REG_OP_B, RegData );
01332     RegData |= FPGA_BIT_VRAM_ENABLE;
01333     Write( FPGA_REG_OP_B, RegData );
01334 
01335     WriteMultiSRMD( FPGA_REG_VRAM_INPUT, 
01336                     m_ApnSensorInfo->m_VerticalPattern.PatternData,
01337                     m_ApnSensorInfo->m_VerticalPattern.NumElements );
01338 
01339     // RAM is now loaded (Disable)
01340     Read( FPGA_REG_OP_B, RegData );
01341     RegData &= ~FPGA_BIT_VRAM_ENABLE;
01342     Write( FPGA_REG_OP_B, RegData );
01343 
01344     return 0;
01345 }
01346 
01347 
01348 long CApnCamera::LoadClampPattern()
01349 {
01350     unsigned short RegData;
01351 
01352     // Prime the RAM (Enable)
01353     Read( FPGA_REG_OP_B, RegData );
01354     RegData |= FPGA_BIT_HCLAMP_ENABLE;
01355     Write( FPGA_REG_OP_B, RegData );
01356 
01357     if ( m_DataBits == Apn_Resolution_SixteenBit )
01358     {
01359         WriteHorizontalPattern( &m_ApnSensorInfo->m_ClampPatternSixteen, 
01360                                 FPGA_REG_HCLAMP_INPUT, 
01361                                 1 );
01362     }
01363     else if ( m_DataBits == Apn_Resolution_TwelveBit )
01364     {
01365         WriteHorizontalPattern( &m_ApnSensorInfo->m_ClampPatternTwelve, 
01366                                 FPGA_REG_HCLAMP_INPUT, 
01367                                 1 );
01368     }
01369 
01370     // RAM is now loaded (Disable)
01371     Read( FPGA_REG_OP_B, RegData );
01372     RegData &= ~FPGA_BIT_HCLAMP_ENABLE;
01373     Write( FPGA_REG_OP_B, RegData );
01374 
01375     return 0;
01376 }
01377 
01378 
01379 long CApnCamera::LoadSkipPattern()
01380 {
01381     unsigned short  RegData;
01382 
01383     // Prime the RAM (Enable)
01384     Read( FPGA_REG_OP_B, RegData );
01385     RegData |= FPGA_BIT_HSKIP_ENABLE;
01386     Write( FPGA_REG_OP_B, RegData );
01387 
01388     if ( m_DataBits == Apn_Resolution_SixteenBit )
01389     {
01390         WriteHorizontalPattern( &m_ApnSensorInfo->m_SkipPatternSixteen, 
01391                                 FPGA_REG_HSKIP_INPUT, 
01392                                 1 );
01393     }
01394     else if ( m_DataBits == Apn_Resolution_TwelveBit )
01395     {
01396         WriteHorizontalPattern( &m_ApnSensorInfo->m_SkipPatternTwelve, 
01397                                 FPGA_REG_HSKIP_INPUT, 
01398                                 1 );
01399     }
01400 
01401     // RAM is now loaded (Disable)
01402     Read( FPGA_REG_OP_B, RegData );
01403     RegData &= ~FPGA_BIT_HSKIP_ENABLE;
01404     Write( FPGA_REG_OP_B, RegData );
01405 
01406     return 0;
01407 }
01408 
01409 
01410 long CApnCamera::LoadRoiPattern( unsigned short binning )
01411 {
01412     unsigned short  RegData;
01413 
01414     // Prime the RAM (Enable)
01415     Read( FPGA_REG_OP_B, RegData );
01416     RegData |= FPGA_BIT_HRAM_ENABLE;
01417     Write( FPGA_REG_OP_B, RegData );
01418 
01419     if ( m_DataBits == Apn_Resolution_SixteenBit )
01420     {
01421         WriteHorizontalPattern( &m_ApnSensorInfo->m_RoiPatternSixteen, 
01422                                 FPGA_REG_HRAM_INPUT, 
01423                                 binning );
01424     }
01425     else if ( m_DataBits == Apn_Resolution_TwelveBit )
01426     {
01427         WriteHorizontalPattern( &m_ApnSensorInfo->m_RoiPatternTwelve, 
01428                                 FPGA_REG_HRAM_INPUT, 
01429                                 binning );
01430     }
01431 
01432     // RAM is now loaded (Disable)
01433     Read( FPGA_REG_OP_B, RegData );
01434     RegData &= ~FPGA_BIT_HRAM_ENABLE;
01435     Write( FPGA_REG_OP_B, RegData );
01436 
01437     return 0;
01438 }
01439 
01440 
01441 long CApnCamera::WriteHorizontalPattern( APN_HPATTERN_FILE *Pattern, 
01442                                          unsigned short RamReg, 
01443                                          unsigned short Binning )
01444 {
01445     unsigned short  i;
01446     unsigned short  DataCount;
01447     unsigned short  *DataArray;
01448     unsigned short  Index;
01449     unsigned short  BinNumber;
01450 
01451 
01452     Index     = 0;
01453     BinNumber = Binning - 1;                // arrays are zero-based
01454 
01455     DataCount = Pattern->RefNumElements +
01456                 Pattern->BinNumElements[BinNumber] +
01457                 Pattern->SigNumElements;
01458 
01459     DataArray = (unsigned short *)malloc(DataCount * sizeof(unsigned short));
01460 
01461     for ( i=0; i<Pattern->RefNumElements; i++ )
01462     {
01463         DataArray[Index] = Pattern->RefPatternData[i];
01464         Index++;
01465     }
01466     
01467     for ( i=0; i<Pattern->BinNumElements[BinNumber]; i++ )
01468     {
01469         DataArray[Index] = Pattern->BinPatternData[BinNumber][i];
01470         Index++;
01471     }
01472 
01473     for ( i=0; i<Pattern->SigNumElements; i++ )
01474     {
01475         DataArray[Index] = Pattern->SigPatternData[i];
01476         Index++;
01477     }
01478 
01479     WriteMultiSRMD( RamReg, DataArray, DataCount );
01480 
01481     // cleanup
01482     free( DataArray );
01483 
01484     return 0;
01485 }
01486 
01487 
01488 long CApnCamera::InitDefaults()
01489 {
01490     unsigned short RegVal;
01491     unsigned short CameraID;
01492     unsigned short ShutterDelay;
01493 
01494     unsigned short PreRoiRows, PostRoiRows;
01495     unsigned short PreRoiVBinning, PostRoiVBinning;
01496     unsigned short UnbinnedRoiY;        // Vertical ROI pixels
01497     
01498 
01499     // Read the Camera ID register
01500     Read( FPGA_REG_CAMERA_ID, CameraID );
01501     CameraID &= FPGA_MASK_CAMERA_ID;
01502 
01503     // Look up the ID and dynamically create the m_ApnSensorInfo object
01504     switch ( CameraID )
01505     {
01506     case APN_ALTA_KAF0401E_CAM_ID:
01507         m_ApnSensorInfo = new CApnCamData_KAF0401E;
01508         break;
01509     case APN_ALTA_KAF1602E_CAM_ID:
01510         m_ApnSensorInfo = new CApnCamData_KAF1602E;
01511         break;
01512     case APN_ALTA_KAF0261E_CAM_ID:
01513         m_ApnSensorInfo = new CApnCamData_KAF0261E;
01514         break;
01515     case APN_ALTA_KAF1301E_CAM_ID:
01516         m_ApnSensorInfo = new CApnCamData_KAF1301E;
01517         break;
01518     case APN_ALTA_KAF1401E_CAM_ID:
01519         m_ApnSensorInfo = new CApnCamData_KAF1401E;
01520         break;
01521     case APN_ALTA_KAF1001E_CAM_ID:
01522         m_ApnSensorInfo = new CApnCamData_KAF1001E;
01523         break;
01524     case APN_ALTA_KAF3200E_CAM_ID:
01525         m_ApnSensorInfo = new CApnCamData_KAF3200E;
01526         break;
01527     case APN_ALTA_KAF4202_CAM_ID:
01528         m_ApnSensorInfo = new CApnCamData_KAF4202;
01529         break;
01530     case APN_ALTA_KAF6303E_CAM_ID:
01531         m_ApnSensorInfo = new CApnCamData_KAF6303E;
01532         break;
01533     case APN_ALTA_KAF16801E_CAM_ID:
01534         m_ApnSensorInfo = new CApnCamData_KAF16801E;
01535         break;
01536     case APN_ALTA_TH7899_CAM_ID:
01537         m_ApnSensorInfo = new CApnCamData_TH7899;
01538         break;
01539         case APN_ALTA_CCD4710LS_CAM_ID:
01540                 m_ApnSensorInfo = new CApnCamData_CCD4710LS;
01541                 break;
01542         case APN_ALTA_CCD4710HS_CAM_ID:
01543                 m_ApnSensorInfo = new CApnCamData_CCD4710HS;
01544                 break;
01545         case APN_ALTA_CCD4240LS_CAM_ID:
01546                 m_ApnSensorInfo = new CApnCamData_CCD4240LS;
01547                 break;
01548         case APN_ALTA_CCD4240HS_CAM_ID:
01549                 m_ApnSensorInfo = new CApnCamData_CCD4240HS;
01550                 break;
01551         case APN_ALTA_CCD5710LS_CAM_ID:
01552                 m_ApnSensorInfo = new CApnCamData_CCD5710LS;
01553                 break;
01554         case APN_ALTA_CCD5710HS_CAM_ID:
01555                 m_ApnSensorInfo = new CApnCamData_CCD5710HS;
01556                 break;
01557         case APN_ALTA_CCD3011LS_CAM_ID:
01558                 m_ApnSensorInfo = new CApnCamData_CCD3011LS;
01559                 break;
01560         case APN_ALTA_CCD3011HS_CAM_ID:
01561                 m_ApnSensorInfo = new CApnCamData_CCD3011HS;
01562                 break;
01563         case APN_ALTA_CCD5520LS_CAM_ID:
01564                 m_ApnSensorInfo = new CApnCamData_CCD5520LS;
01565                 break;
01566         case APN_ALTA_CCD5520HS_CAM_ID:
01567                 m_ApnSensorInfo = new CApnCamData_CCD5520HS;
01568                 break;
01569         case APN_ALTA_CCD4720LS_CAM_ID:
01570                 m_ApnSensorInfo = new CApnCamData_CCD4720LS;
01571                 break;
01572         case APN_ALTA_CCD4720HS_CAM_ID:
01573                 m_ApnSensorInfo = new CApnCamData_CCD4720HS;
01574                 break;
01575         case APN_ALTA_CCD7700LS_CAM_ID:
01576                 m_ApnSensorInfo = new CApnCamData_CCD7700LS;
01577                 break;
01578         case APN_ALTA_CCD7700HS_CAM_ID:
01579                 m_ApnSensorInfo = new CApnCamData_CCD7700HS;
01580                 break;
01581         case APN_ALTA_CCD4710LS2_CAM_ID:
01582                 m_ApnSensorInfo = new CApnCamData_CCD4710LS2;
01583                 break;
01584         case APN_ALTA_CCD4710LS3_CAM_ID:
01585                 m_ApnSensorInfo = new CApnCamData_CCD4710LS3;
01586                 break;
01587         case APN_ALTA_CCD4710LS4_CAM_ID:
01588                 m_ApnSensorInfo = new CApnCamData_CCD4710LS4;
01589                 break;
01590         case APN_ALTA_CCD4710LS5_CAM_ID:
01591                 m_ApnSensorInfo = new CApnCamData_CCD4710LS5;
01592                 break;
01593     default:
01594         return 1;
01595         break;
01596     }
01597 
01598     // we created the object, now set everything
01599     m_ApnSensorInfo->Initialize();
01600 
01601     // Initialize public variables
01602     m_DigitizeOverscan          = false;
01603     m_DataBits                  = Apn_Resolution_SixteenBit;
01604 
01605     // Initialize private variables
01606     m_pvtCameraMode             = Apn_CameraMode_Normal;
01607     m_pvtNetworkTransferMode    = Apn_NetworkMode_Tcp;
01608 
01609     // Initialize variables used for imaging
01610     m_RoiStartX     = 0;
01611     m_RoiStartY     = 0;
01612     m_RoiPixelsH    = m_ApnSensorInfo->m_ImagingColumns;
01613     m_RoiPixelsV    = m_ApnSensorInfo->m_ImagingRows;
01614 
01615     m_RoiBinningH   = 1;
01616     m_RoiBinningV   = 1;
01617         printf ("Camera ID is %u\n",CameraID);
01618     printf("sensor = %s\n",         m_ApnSensorInfo->m_Sensor);
01619     printf("model = %s\n",m_ApnSensorInfo->m_CameraModel);
01620     printf("interline = %u\n",m_ApnSensorInfo->m_InterlineCCD);
01621     printf("serialA = %u\n",m_ApnSensorInfo->m_SupportsSerialA);
01622     printf("serialB = %u\n",m_ApnSensorInfo->m_SupportsSerialB);
01623     printf("ccdtype = %u\n",m_ApnSensorInfo->m_SensorTypeCCD);
01624     printf("Tcolumns = %u\n",m_ApnSensorInfo->m_TotalColumns);
01625     printf("ImgColumns = %u\n",m_ApnSensorInfo->m_ImagingColumns);
01626     printf("ClampColumns = %u\n",m_ApnSensorInfo->m_ClampColumns);
01627     printf("PreRoiSColumns = %u\n",m_ApnSensorInfo->m_PreRoiSkipColumns);
01628     printf("PostRoiSColumns = %u\n",m_ApnSensorInfo->m_PostRoiSkipColumns);
01629     printf("OverscanColumns = %u\n",m_ApnSensorInfo->m_OverscanColumns);
01630     printf("TRows = %u\n",m_ApnSensorInfo->m_TotalRows);
01631     printf("ImgRows = %u\n",m_ApnSensorInfo->m_ImagingRows);
01632     printf("UnderscanRows = %u\n",m_ApnSensorInfo->m_UnderscanRows);
01633     printf("OverscanRows = %u\n",m_ApnSensorInfo->m_OverscanRows);
01634     printf("VFlushBinning = %u\n",m_ApnSensorInfo->m_VFlushBinning);
01635     printf("HFlushDisable = %u\n",m_ApnSensorInfo->m_HFlushDisable);
01636     printf("ShutterCloseDelay = %u\n",m_ApnSensorInfo->m_ShutterCloseDelay);
01637     printf("PixelSizeX = %lf\n",m_ApnSensorInfo->m_PixelSizeX);
01638     printf("PixelSizeY = %lf\n",m_ApnSensorInfo->m_PixelSizeY);
01639     printf("Color = %u\n",m_ApnSensorInfo->m_Color);
01640 //  printf("ReportedGainTwelveBit = %lf\n",m_ApnSensorInfo->m_ReportedGainTwelveBit);
01641     printf("ReportedGainSixteenBit = %lf\n",m_ApnSensorInfo->m_ReportedGainSixteenBit);
01642     printf("MinSuggestedExpTime = %lf\n",m_ApnSensorInfo->m_MinSuggestedExpTime);
01643     printf("CoolingSupported = %u\n",m_ApnSensorInfo->m_CoolingSupported);  
01644     printf("RegulatedCoolingSupported = %u\n",m_ApnSensorInfo->m_RegulatedCoolingSupported);
01645     printf("TempSetPoint = %lf\n",m_ApnSensorInfo->m_TempSetPoint);
01646 //  printf("TempRegRate = %u\n",m_ApnSensorInfo->m_TempRegRate);
01647     printf("TempRampRateOne = %u\n",m_ApnSensorInfo->m_TempRampRateOne);
01648     printf("TempRampRateTwo = %u\n",m_ApnSensorInfo->m_TempRampRateTwo);
01649     printf("TempBackoffPoint = %lf\n",m_ApnSensorInfo->m_TempBackoffPoint);
01650     printf("DefaultGainTwelveBit = %u\n",m_ApnSensorInfo->m_DefaultGainTwelveBit);
01651     printf("DefaultOffsetTwelveBit = %u\n",m_ApnSensorInfo->m_DefaultOffsetTwelveBit);
01652     printf("DefaultRVoltage = %u\n",m_ApnSensorInfo->m_DefaultRVoltage);
01653 
01654 
01655 
01656         printf ("RoiPixelsH is %u\n",m_RoiPixelsH);
01657         printf ("RoiPixelsV is %u\n",m_RoiPixelsV);
01658 
01659 
01660     // Issue a clear command, so the registers are zeroed out
01661     // This will put the camera in a known state for us.
01662     Write( FPGA_REG_COMMAND_B, FPGA_BIT_CMD_CLEAR_ALL );
01663 
01664     // Reset the camera
01665     Write( FPGA_REG_COMMAND_B, FPGA_BIT_CMD_RESET );
01666 
01667     // Load Inversion Masks
01668     Write( FPGA_REG_VRAM_INV_MASK, m_ApnSensorInfo->m_VerticalPattern.Mask );
01669     Write( FPGA_REG_HRAM_INV_MASK, m_ApnSensorInfo->m_RoiPatternSixteen.Mask );
01670 
01671     // Load Pattern Files
01672     LoadVerticalPattern();
01673     LoadClampPattern();
01674     LoadSkipPattern();
01675     LoadRoiPattern( m_RoiBinningH );
01676 
01677     // Program default camera settings
01678     Write( FPGA_REG_CLAMP_COUNT,        m_ApnSensorInfo->m_ClampColumns );  
01679     Write( FPGA_REG_PREROI_SKIP_COUNT,  m_ApnSensorInfo->m_PreRoiSkipColumns ); 
01680     Write( FPGA_REG_ROI_COUNT,          m_ApnSensorInfo->m_ImagingColumns );    
01681     Write( FPGA_REG_POSTROI_SKIP_COUNT, m_ApnSensorInfo->m_PostRoiSkipColumns +
01682                                         m_ApnSensorInfo->m_OverscanColumns );       
01683     
01684     // Since the default state of m_DigitizeOverscan is false, set the count to zero.
01685     Write( FPGA_REG_OVERSCAN_COUNT,     0x0 );  
01686 
01687     // Now calculate the vertical settings
01688     UnbinnedRoiY    = m_RoiPixelsV * m_RoiBinningV;
01689 
01690     PreRoiRows      = m_ApnSensorInfo->m_UnderscanRows + 
01691                       m_RoiStartY;
01692     
01693     PostRoiRows     = m_ApnSensorInfo->m_TotalRows -
01694                       PreRoiRows -
01695                       UnbinnedRoiY;
01696 
01697     PreRoiVBinning  = 1;
01698     PostRoiVBinning = 1;
01699 
01700     // For interline CCDs, set "Fast Dump" mode if the particular array is NOT digitized
01701     if ( m_ApnSensorInfo->m_InterlineCCD )
01702     {
01703         // use the fast dump feature to get rid of the data quickly.
01704         // one row, binning to the original row count
01705         // note that we only are not digitized in arrays 1 and 3
01706         PreRoiVBinning  = PreRoiRows;
01707         PostRoiVBinning = PostRoiRows;
01708 
01709         PreRoiVBinning  |= FPGA_BIT_ARRAY_FASTDUMP;
01710         PostRoiVBinning |= FPGA_BIT_ARRAY_FASTDUMP;
01711 
01712         PreRoiRows  = 1;
01713         PostRoiRows = 1;
01714     }
01715 
01716     // Program the vertical settings
01717     Write( FPGA_REG_A1_ROW_COUNT, PreRoiRows ); 
01718     Write( FPGA_REG_A1_VBINNING,  PreRoiVBinning );
01719     
01720     Write( FPGA_REG_A2_ROW_COUNT, m_RoiPixelsV );   
01721     Write( FPGA_REG_A2_VBINNING,  (m_RoiBinningV | FPGA_BIT_ARRAY_DIGITIZE) );  
01722     
01723     Write( FPGA_REG_A3_ROW_COUNT, PostRoiRows );    
01724     Write( FPGA_REG_A3_VBINNING,  PostRoiVBinning );    
01725 
01726     Write( FPGA_REG_VFLUSH_BINNING, m_ApnSensorInfo->m_VFlushBinning );
01727 
01728     double CloseDelay = (double)m_ApnSensorInfo->m_ShutterCloseDelay / 1000;
01729     ShutterDelay = (unsigned short)
01730         ( (CloseDelay - APN_SHUTTER_CLOSE_DIFF) / APN_TIMER_RESOLUTION );
01731 
01732     Write( FPGA_REG_SHUTTER_CLOSE_DELAY, ShutterDelay );
01733 
01734     Write( FPGA_REG_IMAGE_COUNT,    1 );
01735     Write( FPGA_REG_SEQUENCE_DELAY, 0 );
01736 
01737     if ( m_ApnSensorInfo->m_HFlushDisable )
01738     {
01739         Read( FPGA_REG_OP_A, RegVal );
01740 
01741         RegVal |= FPGA_BIT_DISABLE_H_CLK; 
01742         
01743         Write( FPGA_REG_OP_A, RegVal );
01744     }
01745 
01746     // Reset the camera again
01747     Write( FPGA_REG_COMMAND_B, FPGA_BIT_CMD_RESET );
01748 
01749     // Start flushing
01750     Write( FPGA_REG_COMMAND_A, FPGA_BIT_CMD_FLUSH );
01751 
01752     // If we are a USB2 camera, set all the 12bit variables for the 12bit
01753     // A/D processor
01754     if ( m_CameraInterface == Apn_Interface_USB )
01755     {
01756         InitTwelveBitAD();
01757         write_TwelveBitGain( m_ApnSensorInfo->m_DefaultGainTwelveBit );
01758         WriteTwelveBitOffset();
01759     }
01760 
01761     // Set the Fan State.  Setting the private var first to make sure the write_FanMode
01762     // call thinks we're doing a state transition.
01763     // On write_FanMode return, our state will be Apn_FanMode_Medium
01764     m_pvtFanMode = Apn_FanMode_Off;     // we're going to set this
01765     write_FanMode( Apn_FanMode_Medium );
01766 
01767     // Initialize the LED states and the LED mode.  There is nothing to output
01768     // to the device since we issued our CLEAR early in the init() process, and 
01769     // we are now in a known state.
01770     m_pvtLedStateA  = Apn_LedState_Expose;
01771     m_pvtLedStateB  = Apn_LedState_Expose;
01772     m_pvtLedMode    = Apn_LedMode_EnableAll;
01773 
01774     // Default value for test LED is 0%
01775     m_pvtTestLedBrightness = 0.0;
01776 
01777     // Program our initial cooler values.  The only cooler value that we reset
01778     // at init time is the backoff point.  Everything else is left untouched, and
01779     // state information is determined from the camera controller.
01780     m_pvtCoolerBackoffPoint = m_ApnSensorInfo->m_TempBackoffPoint;
01781     write_CoolerBackoffPoint( m_pvtCoolerBackoffPoint );
01782     Write( FPGA_REG_TEMP_RAMP_DOWN_A,   m_ApnSensorInfo->m_TempRampRateOne );
01783     Write( FPGA_REG_TEMP_RAMP_DOWN_B,   m_ApnSensorInfo->m_TempRampRateTwo );
01784     // the collor code not only determines the m_pvtCoolerEnable state, but
01785     // also implicitly calls UpdateGeneralStatus() as part of read_CoolerStatus()
01786     if ( read_CoolerStatus() == Apn_CoolerStatus_Off )
01787         m_pvtCoolerEnable = false;
01788     else
01789         m_pvtCoolerEnable = true;
01790 
01791     m_pvtImageInProgress    = false;
01792     m_pvtImageReady         = false;
01793     
01794     return 0;
01795 }
01796 
01797 long CApnCamera::InitTwelveBitAD()
01798 {
01799     Write( FPGA_REG_AD_CONFIG_DATA, 0x0028 );
01800     Write( FPGA_REG_COMMAND_B,      FPGA_BIT_CMD_AD_CONFIG );
01801 
01802     return 0;
01803 }
01804 
01805 long CApnCamera::WriteTwelveBitOffset()
01806 {
01807     unsigned short NewVal;
01808     unsigned short StartVal;
01809     unsigned short FirstBit;
01810 
01811 
01812     NewVal      = 0x0;
01813     StartVal    = m_ApnSensorInfo->m_DefaultOffsetTwelveBit & 0xFF;
01814 
01815     for ( int i=0; i<8; i++ )
01816     {
01817         FirstBit = ( StartVal & 0x0001 );
01818         NewVal |= ( FirstBit << (10-i) );
01819         StartVal = StartVal >> 1;
01820     }
01821 
01822     NewVal |= 0x2000;
01823 
01824     Write( FPGA_REG_AD_CONFIG_DATA, NewVal );
01825     Write( FPGA_REG_COMMAND_B,      FPGA_BIT_CMD_AD_CONFIG );
01826 
01827     return 0;
01828 }
01829 
01830 void CApnCamera::UpdateGeneralStatus()
01831 {
01832     unsigned short  StatusReg;
01833     unsigned short  HeatsinkTempReg;
01834     unsigned short  CcdTempReg;
01835     unsigned short  CoolerDriveReg;
01836     unsigned short  VoltageReg;
01837     unsigned short  TdiCounterReg;
01838     unsigned short  SequenceCounterReg;
01839 
01840 
01841 
01842     // Read the general status register of the device
01843     QueryStatusRegs( StatusReg, 
01844                      HeatsinkTempReg, 
01845                      CcdTempReg, 
01846                      CoolerDriveReg,
01847                      VoltageReg,
01848                      TdiCounterReg,
01849                      SequenceCounterReg );
01850 
01851     m_pvtStatusReg  = StatusReg;
01852 
01853     HeatsinkTempReg &= FPGA_MASK_TEMP_PARAMS;
01854     CcdTempReg      &= FPGA_MASK_TEMP_PARAMS;
01855     CoolerDriveReg  &= FPGA_MASK_TEMP_PARAMS;
01856     VoltageReg      &= FPGA_MASK_INPUT_VOLTAGE;
01857 
01858     if ( CoolerDriveReg > 3200 )
01859         m_pvtCoolerDrive = 100.0;
01860     else
01861         m_pvtCoolerDrive = ( (double)(CoolerDriveReg - 600) / 2600.0 ) * 100.0;
01862     
01863     m_pvtCurrentCcdTemp         = ( (CcdTempReg - APN_TEMP_SETPOINT_ZERO_POINT) 
01864                                     * APN_TEMP_DEGREES_PER_BIT );
01865 
01866     m_pvtCurrentHeatsinkTemp    = ( (HeatsinkTempReg - APN_TEMP_HEATSINK_ZERO_POINT) 
01867                                     * APN_TEMP_DEGREES_PER_BIT );
01868     
01869     m_pvtInputVoltage           = VoltageReg * APN_VOLTAGE_RESOLUTION;
01870 
01871     // Update ShutterState
01872     m_pvtShutterState = ( (m_pvtStatusReg & FPGA_BIT_STATUS_SHUTTER_OPEN) != 0 );
01873 }
01874 
01875 
01876 bool CApnCamera::ImageReady()
01877 {
01878     return m_pvtImageReady;
01879 }
01880 
01881 
01882 void CApnCamera::SignalImagingDone()
01883 {
01884     m_pvtImageInProgress = false;
01885 }
01886 
01887 
01888 
01889 
01890 

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